RISC-V SoC drivers for v6.3-mw0
It's all StarFive stuff this time: Their new JH7110 SoC uses a SiFive core complex, and therefore a SiFive cache controller too. That needed a compatible added to both the binding and driver. The JH7110 also has power domains, which are supported by a new driver and a corresponding dt-binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9A3iwAKCRB4tDGHoIJi 0qE4AQDPCcoarT/vLZ28H4wBHPUBxnmU1rut3uNM4f1lIqK0PgD+N6N3xGajmVy0 UzD8/qg2gua94rx/2dmE4PWvun+newk= =Lqa0 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPX3XUACgkQmmx57+YA GNmTrw//amIzDDsnOBOblQMV0yJCpOgj/r6azaYdb2M7a++3ysdUVDnqz9E0VlkE YusfPAg//Fc/6/r6nV6CiCodoprC5g8dkrhFvLUllLnvSQP9Fz/BB99o93aITGUj gqRubCpEnVbsDkinUKDKw8A/RSkMhxsTN3d+JhuZi9RtISUiiNpAGJavut5AsLZS r7ADgNQppcHE02ujdLNszYOZdQgOh00ewKtDWw6RsBGcybTRSuiGnANtaEufvl+W pROapERp/ca8o6odUXaoP7YLFDAHtCbgREdzRtaOtO0HEcP8BKawpJvDHVtTScaQ h5o//DGHKBRDYOVykzAlPdjLXQqvN2vb8Li2SO1DdHvD9Mdjqg0XFKUUIv/7kVu8 uIpat254aGujDsBX+1y+cePSh7UJvjv6KHQz3gVIpfPCcceKXyR7zTrMobC5d2/b ALBgDXhzfy00v/CFKYjBSIskLaLTSx9fz5CRan2xbpo0TpB8o7hb/nCcRJkGOGUW 1LojbM+vdaX/isqxNFAfowCDfBwyLaygvL8HCjT0IKuZ1End9GBuiYDMDfssw1M0 cDepFYy5e2VOfKVhexC2ZTL5n7RDpFy3lVSrVD4gFERZg7iH2UtU4QHHbOujNxe9 yBHIaEFtKJy7244XM3ug8wP6eRDhjo3OFJkMrecdCOQVx3knAUU= =Dfx0 -----END PGP SIGNATURE----- Merge tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.3-mw0 It's all StarFive stuff this time: Their new JH7110 SoC uses a SiFive core complex, and therefore a SiFive cache controller too. That needed a compatible added to both the binding and driver. The JH7110 also has power domains, which are supported by a new driver and a corresponding dt-binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: starfive: Add StarFive JH71XX pmu driver dt-bindings: power: Add starfive,jh7110-pmu soc: sifive: ccache: Add StarFive JH7110 support dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
75dae633c9
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@ -0,0 +1,45 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Power Management Unit
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maintainers:
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- Walker Chen <walker.chen@starfivetech.com>
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description: |
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StarFive JH7110 SoC includes support for multiple power domains which can be
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powered on/off by software based on different application scenes to save power.
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properties:
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compatible:
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enum:
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- starfive,jh7110-pmu
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#power-domain-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#power-domain-cells"
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additionalProperties: false
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examples:
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- |
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pwrc: power-controller@17030000 {
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compatible = "starfive,jh7110-pmu";
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reg = <0x17030000 0x10000>;
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interrupts = <111>;
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#power-domain-cells = <1>;
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};
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@ -38,6 +38,10 @@ properties:
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- sifive,fu540-c000-ccache
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- sifive,fu740-c000-ccache
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- const: cache
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- items:
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- const: starfive,jh7110-ccache
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- const: sifive,ccache0
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- const: cache
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- items:
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- const: microchip,mpfs-ccache
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- const: sifive,fu540-c000-ccache
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@ -85,6 +89,7 @@ allOf:
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contains:
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enum:
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- sifive,fu740-c000-ccache
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- starfive,jh7110-ccache
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- microchip,mpfs-ccache
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then:
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@ -105,7 +110,9 @@ allOf:
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properties:
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compatible:
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contains:
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const: sifive,fu740-c000-ccache
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enum:
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- sifive,fu740-c000-ccache
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- starfive,jh7110-ccache
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then:
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properties:
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|
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13
MAINTAINERS
13
MAINTAINERS
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@ -19913,6 +19913,19 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
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F: drivers/reset/reset-starfive-jh7100.c
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F: include/dt-bindings/reset/starfive-jh7100.h
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STARFIVE SOC DRIVERS
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M: Conor Dooley <conor@kernel.org>
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S: Maintained
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
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F: drivers/soc/starfive/
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STARFIVE JH71XX PMU CONTROLLER DRIVER
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M: Walker Chen <walker.chen@starfivetech.com>
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S: Supported
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F: Documentation/devicetree/bindings/power/starfive*
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F: drivers/soc/starfive/jh71xx_pmu.c
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F: include/dt-bindings/power/starfive,jh7110-pmu.h
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STATIC BRANCH/CALL
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M: Peter Zijlstra <peterz@infradead.org>
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M: Josh Poimboeuf <jpoimboe@kernel.org>
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|
|
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@ -22,6 +22,7 @@ source "drivers/soc/renesas/Kconfig"
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source "drivers/soc/rockchip/Kconfig"
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source "drivers/soc/samsung/Kconfig"
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source "drivers/soc/sifive/Kconfig"
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source "drivers/soc/starfive/Kconfig"
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source "drivers/soc/sunxi/Kconfig"
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source "drivers/soc/tegra/Kconfig"
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source "drivers/soc/ti/Kconfig"
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|
|
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@ -27,7 +27,8 @@ obj-y += qcom/
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obj-y += renesas/
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obj-y += rockchip/
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obj-$(CONFIG_SOC_SAMSUNG) += samsung/
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obj-$(CONFIG_SOC_SIFIVE) += sifive/
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obj-y += sifive/
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obj-$(CONFIG_SOC_STARFIVE) += starfive/
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obj-y += sunxi/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-y += ti/
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|
|
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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if SOC_SIFIVE
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if SOC_SIFIVE || SOC_STARFIVE
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config SIFIVE_CCACHE
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bool "Sifive Composable Cache controller"
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|
|
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0
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config JH71XX_PMU
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bool "Support PMU for StarFive JH71XX Soc"
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depends on PM
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depends on SOC_STARFIVE || COMPILE_TEST
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default SOC_STARFIVE
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select PM_GENERIC_DOMAINS
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help
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Say 'y' here to enable support power domain support.
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In order to meet low power requirements, a Power Management Unit (PMU)
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is designed for controlling power resources in StarFive JH71XX SoCs.
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_JH71XX_PMU) += jh71xx_pmu.o
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@ -0,0 +1,383 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* StarFive JH71XX PMU (Power Management Unit) Controller Driver
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*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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/* register offset */
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#define JH71XX_PMU_SW_TURN_ON_POWER 0x0C
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#define JH71XX_PMU_SW_TURN_OFF_POWER 0x10
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#define JH71XX_PMU_SW_ENCOURAGE 0x44
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#define JH71XX_PMU_TIMER_INT_MASK 0x48
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#define JH71XX_PMU_CURR_POWER_MODE 0x80
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#define JH71XX_PMU_EVENT_STATUS 0x88
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#define JH71XX_PMU_INT_STATUS 0x8C
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/* sw encourage cfg */
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#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
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#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
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#define JH71XX_PMU_SW_ENCOURAGE_DIS_LO 0x0A
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#define JH71XX_PMU_SW_ENCOURAGE_DIS_HI 0xA0
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#define JH71XX_PMU_SW_ENCOURAGE_ON 0xFF
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/* pmu int status */
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#define JH71XX_PMU_INT_SEQ_DONE BIT(0)
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#define JH71XX_PMU_INT_HW_REQ BIT(1)
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#define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2)
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#define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4)
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#define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6)
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#define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0)
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/*
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* The time required for switching power status is based on the time
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* to turn on the largest domain's power, which is at microsecond level
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*/
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#define JH71XX_PMU_TIMEOUT_US 100
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struct jh71xx_domain_info {
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const char * const name;
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unsigned int flags;
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u8 bit;
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};
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struct jh71xx_pmu_match_data {
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const struct jh71xx_domain_info *domain_info;
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int num_domains;
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};
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struct jh71xx_pmu {
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struct device *dev;
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const struct jh71xx_pmu_match_data *match_data;
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void __iomem *base;
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struct generic_pm_domain **genpd;
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struct genpd_onecell_data genpd_data;
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int irq;
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spinlock_t lock; /* protects pmu reg */
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};
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struct jh71xx_pmu_dev {
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const struct jh71xx_domain_info *domain_info;
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struct jh71xx_pmu *pmu;
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struct generic_pm_domain genpd;
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};
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static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
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{
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struct jh71xx_pmu *pmu = pmd->pmu;
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if (!mask)
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return -EINVAL;
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*is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
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return 0;
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}
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static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
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{
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struct jh71xx_pmu *pmu = pmd->pmu;
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unsigned long flags;
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u32 val;
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u32 mode;
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u32 encourage_lo;
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u32 encourage_hi;
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bool is_on;
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int ret;
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ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
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if (ret) {
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dev_dbg(pmu->dev, "unable to get current state for %s\n",
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pmd->genpd.name);
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return ret;
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}
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if (is_on == on) {
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dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
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pmd->genpd.name, on ? "en" : "dis");
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return 0;
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}
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spin_lock_irqsave(&pmu->lock, flags);
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/*
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* The PMU accepts software encourage to switch power mode in the following 2 steps:
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*
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* 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to
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* the bit corresponding to the power domain that will be turned on
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* and writing 0 to the others.
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* Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by
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* writing 1 to the bit corresponding to the power domain that will be
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* turned off and writing 0 to the others.
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*/
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if (on) {
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mode = JH71XX_PMU_SW_TURN_ON_POWER;
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encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO;
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encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI;
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} else {
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mode = JH71XX_PMU_SW_TURN_OFF_POWER;
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encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO;
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encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
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}
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writel(mask, pmu->base + mode);
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/*
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* 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
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* First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset
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* the state machine which parses the command sequence. This register must be
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* written every time software wants to power on/off a domain.
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* Then write the lower bits of the command sequence, followed by the upper
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* bits. The sequence differs between powering on & off a domain.
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*/
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writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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spin_unlock_irqrestore(&pmu->lock, flags);
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/* Wait for the power domain bit to be enabled / disabled */
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if (on) {
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ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
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val, val & mask,
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1, JH71XX_PMU_TIMEOUT_US);
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} else {
|
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ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
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val, !(val & mask),
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1, JH71XX_PMU_TIMEOUT_US);
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}
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if (ret) {
|
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dev_err(pmu->dev, "%s: failed to power %s\n",
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pmd->genpd.name, on ? "on" : "off");
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return -ETIMEDOUT;
|
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}
|
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|
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return 0;
|
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}
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static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
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{
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struct jh71xx_pmu_dev *pmd = container_of(genpd,
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struct jh71xx_pmu_dev, genpd);
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u32 pwr_mask = BIT(pmd->domain_info->bit);
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return jh71xx_pmu_set_state(pmd, pwr_mask, true);
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}
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static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
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{
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struct jh71xx_pmu_dev *pmd = container_of(genpd,
|
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struct jh71xx_pmu_dev, genpd);
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u32 pwr_mask = BIT(pmd->domain_info->bit);
|
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|
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return jh71xx_pmu_set_state(pmd, pwr_mask, false);
|
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}
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|
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static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
|
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{
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&pmu->lock, flags);
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val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
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||||
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||||
if (enable)
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val &= ~mask;
|
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else
|
||||
val |= mask;
|
||||
|
||||
writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
|
||||
spin_unlock_irqrestore(&pmu->lock, flags);
|
||||
}
|
||||
|
||||
static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
|
||||
{
|
||||
struct jh71xx_pmu *pmu = data;
|
||||
u32 val;
|
||||
|
||||
val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
|
||||
|
||||
if (val & JH71XX_PMU_INT_SEQ_DONE)
|
||||
dev_dbg(pmu->dev, "sequence done.\n");
|
||||
if (val & JH71XX_PMU_INT_HW_REQ)
|
||||
dev_dbg(pmu->dev, "hardware encourage requestion.\n");
|
||||
if (val & JH71XX_PMU_INT_SW_FAIL)
|
||||
dev_err(pmu->dev, "software encourage fail.\n");
|
||||
if (val & JH71XX_PMU_INT_HW_FAIL)
|
||||
dev_err(pmu->dev, "hardware encourage fail.\n");
|
||||
if (val & JH71XX_PMU_INT_PCH_FAIL)
|
||||
dev_err(pmu->dev, "p-channel fail event.\n");
|
||||
|
||||
/* clear interrupts */
|
||||
writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
|
||||
writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
|
||||
{
|
||||
struct jh71xx_pmu_dev *pmd;
|
||||
u32 pwr_mask;
|
||||
int ret;
|
||||
bool is_on = false;
|
||||
|
||||
pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL);
|
||||
if (!pmd)
|
||||
return -ENOMEM;
|
||||
|
||||
pmd->domain_info = &pmu->match_data->domain_info[index];
|
||||
pmd->pmu = pmu;
|
||||
pwr_mask = BIT(pmd->domain_info->bit);
|
||||
|
||||
pmd->genpd.name = pmd->domain_info->name;
|
||||
pmd->genpd.flags = pmd->domain_info->flags;
|
||||
|
||||
ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on);
|
||||
if (ret)
|
||||
dev_warn(pmu->dev, "unable to get current state for %s\n",
|
||||
pmd->genpd.name);
|
||||
|
||||
pmd->genpd.power_on = jh71xx_pmu_on;
|
||||
pmd->genpd.power_off = jh71xx_pmu_off;
|
||||
pm_genpd_init(&pmd->genpd, NULL, !is_on);
|
||||
|
||||
pmu->genpd_data.domains[index] = &pmd->genpd;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jh71xx_pmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct jh71xx_pmu_match_data *match_data;
|
||||
struct jh71xx_pmu *pmu;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
|
||||
if (!pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
pmu->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pmu->base))
|
||||
return PTR_ERR(pmu->base);
|
||||
|
||||
pmu->irq = platform_get_irq(pdev, 0);
|
||||
if (pmu->irq < 0)
|
||||
return pmu->irq;
|
||||
|
||||
ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
|
||||
0, pdev->name, pmu);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to request irq\n");
|
||||
|
||||
match_data = of_device_get_match_data(dev);
|
||||
if (!match_data)
|
||||
return -EINVAL;
|
||||
|
||||
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
|
||||
sizeof(struct generic_pm_domain *),
|
||||
GFP_KERNEL);
|
||||
if (!pmu->genpd)
|
||||
return -ENOMEM;
|
||||
|
||||
pmu->dev = dev;
|
||||
pmu->match_data = match_data;
|
||||
pmu->genpd_data.domains = pmu->genpd;
|
||||
pmu->genpd_data.num_domains = match_data->num_domains;
|
||||
|
||||
for (i = 0; i < match_data->num_domains; i++) {
|
||||
ret = jh71xx_pmu_init_domain(pmu, i);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize power domain\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
spin_lock_init(&pmu->lock);
|
||||
jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
|
||||
|
||||
ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register genpd driver: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "registered %u power domains\n", i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct jh71xx_domain_info jh7110_power_domains[] = {
|
||||
[JH7110_PD_SYSTOP] = {
|
||||
.name = "SYSTOP",
|
||||
.bit = 0,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[JH7110_PD_CPU] = {
|
||||
.name = "CPU",
|
||||
.bit = 1,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[JH7110_PD_GPUA] = {
|
||||
.name = "GPUA",
|
||||
.bit = 2,
|
||||
},
|
||||
[JH7110_PD_VDEC] = {
|
||||
.name = "VDEC",
|
||||
.bit = 3,
|
||||
},
|
||||
[JH7110_PD_VOUT] = {
|
||||
.name = "VOUT",
|
||||
.bit = 4,
|
||||
},
|
||||
[JH7110_PD_ISP] = {
|
||||
.name = "ISP",
|
||||
.bit = 5,
|
||||
},
|
||||
[JH7110_PD_VENC] = {
|
||||
.name = "VENC",
|
||||
.bit = 6,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct jh71xx_pmu_match_data jh7110_pmu = {
|
||||
.num_domains = ARRAY_SIZE(jh7110_power_domains),
|
||||
.domain_info = jh7110_power_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id jh71xx_pmu_of_match[] = {
|
||||
{
|
||||
.compatible = "starfive,jh7110-pmu",
|
||||
.data = (void *)&jh7110_pmu,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver jh71xx_pmu_driver = {
|
||||
.probe = jh71xx_pmu_probe,
|
||||
.driver = {
|
||||
.name = "jh71xx-pmu",
|
||||
.of_match_table = jh71xx_pmu_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(jh71xx_pmu_driver);
|
||||
|
||||
MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
|
||||
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
* Author: Walker Chen <walker.chen@starfivetech.com>
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_JH7110_POWER_H__
|
||||
|
||||
#define JH7110_PD_SYSTOP 0
|
||||
#define JH7110_PD_CPU 1
|
||||
#define JH7110_PD_GPUA 2
|
||||
#define JH7110_PD_VDEC 3
|
||||
#define JH7110_PD_VOUT 4
|
||||
#define JH7110_PD_ISP 5
|
||||
#define JH7110_PD_VENC 6
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue