drm/i915: Use preferred kernel types in i915_gem_gtt.c
Make checkpatch happy and make the use of u32/u64 consistent throughout i915_gem_gtt.[ch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170215084357.19977-23-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
57202f47af
commit
75c7b0b862
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@ -888,7 +888,7 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
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static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
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struct sg_table *pages,
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uint64_t start,
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u64 start,
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enum i915_cache_level cache_level,
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u32 unused)
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{
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@ -1162,25 +1162,25 @@ unwind:
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static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
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struct i915_page_directory_pointer *pdp,
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uint64_t start, uint64_t length,
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u64 start, u64 length,
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gen8_pte_t scratch_pte,
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struct seq_file *m)
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{
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struct i915_page_directory *pd;
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uint32_t pdpe;
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u32 pdpe;
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gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
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struct i915_page_table *pt;
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uint64_t pd_len = length;
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uint64_t pd_start = start;
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uint32_t pde;
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u64 pd_len = length;
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u64 pd_start = start;
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u32 pde;
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if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd)
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continue;
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seq_printf(m, "\tPDPE #%d\n", pdpe);
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gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
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uint32_t pte;
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u32 pte;
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gen8_pte_t *pt_vaddr;
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if (pd->page_table[pde] == ppgtt->base.scratch_pt)
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@ -1188,10 +1188,9 @@ static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
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pt_vaddr = kmap_atomic_px(pt);
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for (pte = 0; pte < GEN8_PTES; pte += 4) {
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uint64_t va =
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(pdpe << GEN8_PDPE_SHIFT) |
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(pde << GEN8_PDE_SHIFT) |
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(pte << GEN8_PTE_SHIFT);
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u64 va = (pdpe << GEN8_PDPE_SHIFT |
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pde << GEN8_PDE_SHIFT |
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pte << GEN8_PTE_SHIFT);
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int i;
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bool found = false;
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@ -1225,7 +1224,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
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if (!USES_FULL_48BIT_PPGTT(vm->i915)) {
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gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m);
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} else {
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uint64_t pml4e;
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u64 pml4e;
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struct i915_pml4 *pml4 = &ppgtt->pml4;
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struct i915_page_directory_pointer *pdp;
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@ -1407,7 +1406,7 @@ static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt,
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/* Write all the page tables found in the ppgtt structure to incrementing page
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* directories. */
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static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
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uint32_t start, uint32_t length)
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u32 start, u32 length)
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{
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struct i915_page_table *pt;
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unsigned int pde;
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@ -1419,7 +1418,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
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wmb();
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}
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static inline uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
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static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
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{
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GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
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return ppgtt->pd.base.ggtt_offset << 10;
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@ -1513,7 +1512,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
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static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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uint32_t ecochk, ecobits;
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u32 ecochk, ecobits;
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enum intel_engine_id id;
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ecobits = I915_READ(GAC_ECO_BITS);
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@ -1537,7 +1536,7 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
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static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
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{
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uint32_t ecochk, gab_ctl, ecobits;
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u32 ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
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@ -1589,8 +1588,9 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
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static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
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struct sg_table *pages,
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uint64_t start,
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enum i915_cache_level cache_level, u32 flags)
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u64 start,
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enum i915_cache_level cache_level,
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u32 flags)
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{
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struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
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unsigned first_entry = start >> PAGE_SHIFT;
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@ -1690,7 +1690,7 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
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struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
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struct i915_page_directory *pd = &ppgtt->pd;
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struct i915_page_table *pt;
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uint32_t pde;
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u32 pde;
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drm_mm_remove_node(&ppgtt->node);
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@ -1748,10 +1748,10 @@ static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
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}
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static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
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uint64_t start, uint64_t length)
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u64 start, u64 length)
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{
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struct i915_page_table *unused;
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uint32_t pde;
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u32 pde;
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gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
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ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
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@ -2045,7 +2045,7 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
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static void gen8_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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uint64_t offset,
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u64 offset,
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enum i915_cache_level level,
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u32 unused)
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{
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@ -2060,8 +2060,9 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
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static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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enum i915_cache_level level, u32 unused)
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u64 start,
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enum i915_cache_level level,
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u32 unused)
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{
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struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
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struct sgt_iter sgt_iter;
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@ -2086,7 +2087,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
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struct insert_entries {
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struct i915_address_space *vm;
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struct sg_table *st;
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uint64_t start;
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u64 start;
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enum i915_cache_level level;
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u32 flags;
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};
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@ -2101,7 +2102,7 @@ static int gen8_ggtt_insert_entries__cb(void *_arg)
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static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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u64 start,
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enum i915_cache_level level,
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u32 flags)
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{
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@ -2111,7 +2112,7 @@ static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
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static void gen6_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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uint64_t offset,
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u64 offset,
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enum i915_cache_level level,
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u32 flags)
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{
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@ -2132,8 +2133,9 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm,
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*/
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static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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enum i915_cache_level level, u32 flags)
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u64 start,
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enum i915_cache_level level,
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u32 flags)
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{
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struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
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gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
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@ -2152,12 +2154,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
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}
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static void nop_clear_range(struct i915_address_space *vm,
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uint64_t start, uint64_t length)
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u64 start, u64 length)
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{
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}
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static void gen8_ggtt_clear_range(struct i915_address_space *vm,
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uint64_t start, uint64_t length)
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u64 start, u64 length)
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{
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struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
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unsigned first_entry = start >> PAGE_SHIFT;
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@ -2179,8 +2181,7 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
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}
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static void gen6_ggtt_clear_range(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length)
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u64 start, u64 length)
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{
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struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
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unsigned first_entry = start >> PAGE_SHIFT;
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@ -2204,7 +2205,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
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static void i915_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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uint64_t offset,
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u64 offset,
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enum i915_cache_level cache_level,
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u32 unused)
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{
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@ -2216,8 +2217,9 @@ static void i915_ggtt_insert_page(struct i915_address_space *vm,
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static void i915_ggtt_insert_entries(struct i915_address_space *vm,
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struct sg_table *pages,
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uint64_t start,
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enum i915_cache_level cache_level, u32 unused)
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u64 start,
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enum i915_cache_level cache_level,
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u32 unused)
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{
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unsigned int flags = (cache_level == I915_CACHE_NONE) ?
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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@ -2226,8 +2228,7 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
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}
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static void i915_ggtt_clear_range(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length)
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u64 start, u64 length)
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{
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intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
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}
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@ -2641,7 +2642,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
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* writing this data shouldn't be harmful even in those cases. */
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static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
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{
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uint64_t pat;
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u64 pat;
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pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
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GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
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@ -2676,7 +2677,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
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static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
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{
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uint64_t pat;
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u64 pat;
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/*
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* Map WB on BDW to snooped on CHV.
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@ -3073,7 +3074,7 @@ static noinline struct sg_table *
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intel_rotate_pages(struct intel_rotation_info *rot_info,
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struct drm_i915_gem_object *obj)
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{
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const size_t n_pages = obj->base.size / PAGE_SIZE;
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const unsigned long n_pages = obj->base.size / PAGE_SIZE;
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unsigned int size = intel_rotation_info_size(rot_info);
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struct sgt_iter sgt_iter;
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dma_addr_t dma_addr;
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@ -53,11 +53,11 @@
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struct drm_i915_file_private;
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struct drm_i915_fence_reg;
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typedef uint32_t gen6_pte_t;
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typedef uint64_t gen8_pte_t;
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typedef uint64_t gen8_pde_t;
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typedef uint64_t gen8_ppgtt_pdpe_t;
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typedef uint64_t gen8_ppgtt_pml4e_t;
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typedef u32 gen6_pte_t;
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typedef u64 gen8_pte_t;
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typedef u64 gen8_pde_t;
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typedef u64 gen8_ppgtt_pdpe_t;
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typedef u64 gen8_ppgtt_pml4e_t;
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#define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
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@ -143,7 +143,7 @@ typedef uint64_t gen8_ppgtt_pml4e_t;
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#define GEN8_PPAT_WC (1<<0)
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#define GEN8_PPAT_UC (0<<0)
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#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
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#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
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#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
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struct sg_table;
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@ -210,7 +210,7 @@ struct i915_page_dma {
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/* For gen6/gen7 only. This is the offset in the GGTT
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* where the page directory entries for PPGTT begin
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*/
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uint32_t ggtt_offset;
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u32 ggtt_offset;
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};
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};
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@ -305,20 +305,19 @@ struct i915_address_space {
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/* flags for pte_encode */
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#define PTE_READ_ONLY (1<<0)
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int (*allocate_va_range)(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length);
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u64 start, u64 length);
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void (*clear_range)(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length);
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u64 start, u64 length);
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void (*insert_page)(struct i915_address_space *vm,
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dma_addr_t addr,
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uint64_t offset,
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u64 offset,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*insert_entries)(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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enum i915_cache_level cache_level, u32 flags);
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u64 start,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*cleanup)(struct i915_address_space *vm);
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/** Unmap an object from an address space. This usually consists of
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* setting the valid PTE entries to a reserved scratch page. */
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@ -411,9 +410,9 @@ struct i915_hw_ppgtt {
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(pt = (pd)->page_table[iter], true); \
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++iter)
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static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
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static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
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{
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const uint32_t mask = NUM_PTE(pde_shift) - 1;
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const u32 mask = NUM_PTE(pde_shift) - 1;
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return (address >> PAGE_SHIFT) & mask;
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}
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@ -422,11 +421,10 @@ static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
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* does not cross a page table boundary, so the max value would be
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* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
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*/
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static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
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uint32_t pde_shift)
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static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
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{
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const uint64_t mask = ~((1ULL << pde_shift) - 1);
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uint64_t end;
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const u64 mask = ~((1ULL << pde_shift) - 1);
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u64 end;
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WARN_ON(length == 0);
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WARN_ON(offset_in_page(addr|length));
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@ -439,22 +437,22 @@ static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
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return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
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}
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static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
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static inline u32 i915_pde_index(u64 addr, u32 shift)
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{
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return (addr >> shift) & I915_PDE_MASK;
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}
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static inline uint32_t gen6_pte_index(uint32_t addr)
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static inline u32 gen6_pte_index(u32 addr)
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{
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return i915_pte_index(addr, GEN6_PDE_SHIFT);
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}
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static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
|
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static inline u32 gen6_pte_count(u32 addr, u32 length)
|
||||
{
|
||||
return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
|
||||
}
|
||||
|
||||
static inline uint32_t gen6_pde_index(uint32_t addr)
|
||||
static inline u32 gen6_pde_index(u32 addr)
|
||||
{
|
||||
return i915_pde_index(addr, GEN6_PDE_SHIFT);
|
||||
}
|
||||
|
|
@ -487,27 +485,27 @@ static inline uint32_t gen6_pde_index(uint32_t addr)
|
|||
temp = min(temp - start, length); \
|
||||
start += temp, length -= temp; }), ++iter)
|
||||
|
||||
static inline uint32_t gen8_pte_index(uint64_t address)
|
||||
static inline u32 gen8_pte_index(u64 address)
|
||||
{
|
||||
return i915_pte_index(address, GEN8_PDE_SHIFT);
|
||||
}
|
||||
|
||||
static inline uint32_t gen8_pde_index(uint64_t address)
|
||||
static inline u32 gen8_pde_index(u64 address)
|
||||
{
|
||||
return i915_pde_index(address, GEN8_PDE_SHIFT);
|
||||
}
|
||||
|
||||
static inline uint32_t gen8_pdpe_index(uint64_t address)
|
||||
static inline u32 gen8_pdpe_index(u64 address)
|
||||
{
|
||||
return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t gen8_pml4e_index(uint64_t address)
|
||||
static inline u32 gen8_pml4e_index(u64 address)
|
||||
{
|
||||
return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
|
||||
}
|
||||
|
||||
static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
|
||||
static inline u64 gen8_pte_count(u64 address, u64 length)
|
||||
{
|
||||
return i915_pte_count(address, length, GEN8_PDE_SHIFT);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue