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sh_eth: fix TRSCER mask for R7S72100 

According  to  the RZ/A1H Group, RZ/A1M Group User's Manual: Hardware,
Rev. 4.00, the TRSCER register has bit 9 reserved, hence we can't use
the driver's default TRSCER mask.  Add the explicit initializer for
sh_eth_cpu_data::trscer_err_mask for R7S72100.

Fixes: db893473d3 ("sh_eth: Add support for r7s72100")
Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sergey Shtylyov 2021-02-28 23:26:34 +03:00 committed by David S. Miller
parent 8c91bc3d44
commit 75be7fb7f9
1 changed files with 2 additions and 0 deletions
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2
drivers/net/ethernet/renesas/sh_eth.c
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@ -560,6 +560,8 @@ static struct sh_eth_cpu_data r7s72100_data = {
EESR_TDE,
.fdr_value = 0x0000070f,
.trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
.no_psr = 1,
.apr = 1,
.mpr = 1,