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clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors 

The arch timer driver never reads the various TVAL registers, only
writes to them. It is thus pointless to provide accessors
for them and to implement errata workarounds.

Drop these read-side accessors, and add a couple of BUG() statements
for the time being. These statements will be removed further down
the line.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-3-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
This commit is contained in:
Marc Zyngier 2021-10-17 13:42:10 +01:00 committed by Jianping Liu
parent ea9b4217be
commit 75a5a259c0
3 changed files with 0 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/include/asm/arch_timer.h
View File

@ -65,9 +65,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
break; break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
break;
default: default:
BUILD_BUG(); BUILD_BUG();
} }
@ -76,9 +73,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
break; break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
break;
default: default:
BUILD_BUG(); BUILD_BUG();
} }

17
arch/arm64/include/asm/arch_timer.h
View File

@ -52,8 +52,6 @@ struct arch_timer_erratum_workaround {
enum arch_timer_erratum_match_type match_type; enum arch_timer_erratum_match_type match_type;
const void *id; const void *id;
const char *desc; const char *desc;
u32 (*read_cntp_tval_el0)(void);
u32 (*read_cntv_tval_el0)(void);
u64 (*read_cntpct_el0)(void); u64 (*read_cntpct_el0)(void);
u64 (*read_cntvct_el0)(void); u64 (*read_cntvct_el0)(void);
int (*set_next_event_phys)(unsigned long, struct clock_event_device *); int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
@ -64,17 +62,6 @@ struct arch_timer_erratum_workaround {
DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
timer_unstable_counter_workaround); timer_unstable_counter_workaround);
/* inline sysreg accessors that make erratum_handler() work */
static inline notrace u32 arch_timer_read_cntp_tval_el0(void)
{
return read_sysreg(cntp_tval_el0);
}
static inline notrace u32 arch_timer_read_cntv_tval_el0(void)
{
return read_sysreg(cntv_tval_el0);
}
static inline notrace u64 arch_timer_read_cntpct_el0(void) static inline notrace u64 arch_timer_read_cntpct_el0(void)
{ {
return read_sysreg(cntpct_el0); return read_sysreg(cntpct_el0);
@ -140,8 +127,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntp_ctl_el0); return read_sysreg(cntp_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntp_tval_el0);
default: default:
BUILD_BUG(); BUILD_BUG();
} }
@ -149,8 +134,6 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntv_ctl_el0); return read_sysreg(cntv_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntv_tval_el0);
default: default:
BUILD_BUG(); BUILD_BUG();
} }

44
drivers/clocksource/arm_arch_timer.c
View File

@ -129,9 +129,6 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
val = readl_relaxed(timer->base + CNTP_CTL); val = readl_relaxed(timer->base + CNTP_CTL);
break; break;
case ARCH_TIMER_REG_TVAL:
val = readl_relaxed(timer->base + CNTP_TVAL);
break;
default: default:
BUILD_BUG(); BUILD_BUG();
} }
@ -141,9 +138,6 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
val = readl_relaxed(timer->base + CNTV_CTL); val = readl_relaxed(timer->base + CNTV_CTL);
break; break;
case ARCH_TIMER_REG_TVAL:
val = readl_relaxed(timer->base + CNTV_TVAL);
break;
default: default:
BUILD_BUG(); BUILD_BUG();
} }
@ -231,16 +225,6 @@ struct ate_acpi_oem_info {
_new; \ _new; \
}) })
static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
static u64 notrace fsl_a008585_read_cntpct_el0(void) static u64 notrace fsl_a008585_read_cntpct_el0(void)
{ {
return __fsl_a008585_read_reg(cntpct_el0); return __fsl_a008585_read_reg(cntpct_el0);
@ -277,16 +261,6 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
_new; \ _new; \
}) })
static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
{
return __hisi_161010101_read_reg(cntp_tval_el0);
}
static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
{
return __hisi_161010101_read_reg(cntv_tval_el0);
}
static u64 notrace hisi_161010101_read_cntpct_el0(void) static u64 notrace hisi_161010101_read_cntpct_el0(void)
{ {
return __hisi_161010101_read_reg(cntpct_el0); return __hisi_161010101_read_reg(cntpct_el0);
@ -371,16 +345,6 @@ static u64 notrace sun50i_a64_read_cntvct_el0(void)
{ {
return __sun50i_a64_read_reg(cntvct_el0); return __sun50i_a64_read_reg(cntvct_el0);
} }
static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
{
return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
}
static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
{
return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
}
#endif #endif
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
@ -430,8 +394,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.match_type = ate_match_dt, .match_type = ate_match_dt,
.id = "fsl,erratum-a008585", .id = "fsl,erratum-a008585",
.desc = "Freescale erratum a005858", .desc = "Freescale erratum a005858",
.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
.read_cntpct_el0 = fsl_a008585_read_cntpct_el0, .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
.read_cntvct_el0 = fsl_a008585_read_cntvct_el0, .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
.set_next_event_phys = erratum_set_next_event_tval_phys, .set_next_event_phys = erratum_set_next_event_tval_phys,
@ -443,8 +405,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.match_type = ate_match_dt, .match_type = ate_match_dt,
.id = "hisilicon,erratum-161010101", .id = "hisilicon,erratum-161010101",
.desc = "HiSilicon erratum 161010101", .desc = "HiSilicon erratum 161010101",
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
.read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
.set_next_event_phys = erratum_set_next_event_tval_phys, .set_next_event_phys = erratum_set_next_event_tval_phys,
@ -454,8 +414,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.match_type = ate_match_acpi_oem_info, .match_type = ate_match_acpi_oem_info,
.id = hisi_161010101_oem_info, .id = hisi_161010101_oem_info,
.desc = "HiSilicon erratum 161010101", .desc = "HiSilicon erratum 161010101",
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
.read_cntpct_el0 = hisi_161010101_read_cntpct_el0, .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0, .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
.set_next_event_phys = erratum_set_next_event_tval_phys, .set_next_event_phys = erratum_set_next_event_tval_phys,
@ -476,8 +434,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.match_type = ate_match_dt, .match_type = ate_match_dt,
.id = "allwinner,erratum-unknown1", .id = "allwinner,erratum-unknown1",
.desc = "Allwinner erratum UNKNOWN1", .desc = "Allwinner erratum UNKNOWN1",
.read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
.read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
.read_cntpct_el0 = sun50i_a64_read_cntpct_el0, .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
.read_cntvct_el0 = sun50i_a64_read_cntvct_el0, .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
.set_next_event_phys = erratum_set_next_event_tval_phys, .set_next_event_phys = erratum_set_next_event_tval_phys,