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drm/amd/display: To update backlight restore mechanism 

[Why]
Cached backlight is never being updated since panel_cntl specific
registers were moved from abm to panel_cntl.

[How]
Update cached backlight in set_abm_immediate_disable as what we used to
do. Also, update the priority of backlight restore mechanism so that
cached backlight has the highest priority since it is always correct.

Signed-off-by: Camille Cho <Camille.Cho@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Camille Cho 2020-11-12 15:33:19 +08:00 committed by Alex Deucher
parent eaae693835
commit 7530d91463
2 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
View File

@ -108,25 +108,17 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
*/
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
if (value == 0 || value == 1) {
if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
REG_WRITE(BL_PWM_CNTL,
panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
REG_WRITE(BL_PWM_CNTL2,
panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
REG_WRITE(BL_PWM_PERIOD_CNTL,
panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
REG_UPDATE(PWRSEQ_REF_DIV,
BL_PWM_REF_DIV,
panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else {
/* TODO: Note: This should not really happen since VBIOS
* should have initialized PWM registers on boot.
*/
REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
}
} else {
if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
REG_WRITE(BL_PWM_CNTL,
panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
REG_WRITE(BL_PWM_CNTL2,
panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
REG_WRITE(BL_PWM_PERIOD_CNTL,
panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
REG_UPDATE(PWRSEQ_REF_DIV,
BL_PWM_REF_DIV,
panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else if ((value != 0) && (value != 1)) {
panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
REG_READ(BL_PWM_CNTL);
panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
@ -136,6 +128,12 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else {
/* TODO: Note: This should not really happen since VBIOS
* should have initialized PWM registers on boot.
*/
REG_WRITE(BL_PWM_CNTL, 0x8000FA00);
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
}
// Have driver take backlight control

4
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
View File

@ -171,9 +171,11 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
return;
}
if (abm && panel_cntl)
if (abm && panel_cntl) {
dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,
panel_cntl->inst);
panel_cntl->funcs->store_backlight_level(panel_cntl);
}
}
void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)