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ARM: dts: aspeed: add SPI controller bindings 

Let's define the SPI controllers in the Aspeed SoCs AST2500 and
AST2400 and also enable these, as well as the chips, on the associated
platforms.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Cédric Le Goater 2017-03-01 15:26:42 +01:00 committed by Joel Stanley
parent c1ae3cfa0e
commit 74dc3cd32e
4 changed files with 128 additions and 0 deletions
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20
arch/arm/boot/dts/aspeed-ast2500-evb.dts
View File

@ -20,6 +20,26 @@
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
};
};
&spi1 {
status = "okay";
flash@0 {
status = "okay";
label = "pnor";
};
};
&spi2 {
status = "okay";
};
&uart5 {
status = "okay";
};

16
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
View File

@ -31,6 +31,22 @@
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
};
};
&spi {
status = "okay";
flash@0 {
status = "okay";
label = "pnor";
};
};
&uart5 {
status = "okay";
};

29
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -33,6 +33,35 @@
#size-cells = <1>;
ranges;
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0x94
0x20000000 0x02000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
status = "disabled";
interrupts = <19>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi: flash-controller@1e630000 {
reg = < 0x1e630000 0x18
0x30000000 0x02000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;

63
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -24,6 +24,69 @@
#size-cells = <1>;
ranges;
fmc: flash-controller@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
status = "disabled";
interrupts = <19>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi1: flash-controller@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi2: flash-controller@1e631000 {
reg = < 0x1e631000 0xc4
0x38000000 0x08000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
status = "disabled";
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;