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ARM: dts: mediatek: add MT2701 basic support 

This adds basic chip support for Mediatek 2701.

Signed-off-by: Erin Lo <erin.lo@mediatek.com>
[matthias.bgg@gmail.com: Fixed reg address of mt2701-timer]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Erin Lo 2015-10-20 14:34:31 +08:00 committed by Matthias Brugger
parent 02eca17376
commit 74d25721ee
4 changed files with 177 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -771,6 +771,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
dove-dove-db.dtb \
dove-sbc-a510.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt2701-evb.dtb \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \

29
arch/arm/boot/dts/mt2701-evb.dts Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Erin Lo <erin.lo@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "mt2701.dtsi"
/ {
model = "MediaTek MT2701 evaluation board";
compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
memory {
reg = <0 0x80000000 0 0x40000000>;
};
};
&uart0 {
status = "okay";
};

146
arch/arm/boot/dts/mt2701.dtsi Normal file
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@ -0,0 +1,146 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Erin.Lo <erin.lo@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
/ {
compatible = "mediatek,mt2701";
interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
};
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
rtc_clk: dummy32k {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
timer: timer@10008000 {
compatible = "mediatek,mt2701-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200100 0 0x1c>;
};
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x1000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt2701-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};

1
arch/arm/mach-mediatek/mediatek.c
View File

@ -44,6 +44,7 @@ static void __init mediatek_timer_init(void)
};
static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt2701",
"mediatek,mt6589",
"mediatek,mt6592",
"mediatek,mt8127",