[media] v4l: omap3isp: Fix data lane shift configuration
The data-shift DT property speficies the number of bits to be shifted, but the driver still interprets the value as a multiple of two bits as used by now removed platform data support. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -449,7 +449,7 @@ void omap3isp_configure_bridge(struct isp_device *isp,
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case CCDC_INPUT_PARALLEL:
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ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
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ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
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shift += parcfg->data_lane_shift * 2;
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shift += parcfg->data_lane_shift;
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break;
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case CCDC_INPUT_CSI2A:
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@ -2421,7 +2421,7 @@ static int ccdc_link_validate(struct v4l2_subdev *sd,
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&((struct isp_bus_cfg *)
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media_entity_to_v4l2_subdev(link->source->entity)
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->host_priv)->bus.parallel;
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parallel_shift = parcfg->data_lane_shift * 2;
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parallel_shift = parcfg->data_lane_shift;
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} else {
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parallel_shift = 0;
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}
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@ -33,9 +33,9 @@ enum isp_interface_type {
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* struct isp_parallel_cfg - Parallel interface configuration
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* @data_lane_shift: Data lane shifter
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* 0 - CAMEXT[13:0] -> CAM[13:0]
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* 1 - CAMEXT[13:2] -> CAM[11:0]
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* 2 - CAMEXT[13:4] -> CAM[9:0]
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* 3 - CAMEXT[13:6] -> CAM[7:0]
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* 2 - CAMEXT[13:2] -> CAM[11:0]
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* 4 - CAMEXT[13:4] -> CAM[9:0]
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* 6 - CAMEXT[13:6] -> CAM[7:0]
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* @clk_pol: Pixel clock polarity
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* 0 - Sample on rising edge, 1 - Sample on falling edge
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* @hs_pol: Horizontal synchronization polarity
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@ -48,7 +48,7 @@ enum isp_interface_type {
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* 0 - Normal, 1 - One's complement
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*/
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struct isp_parallel_cfg {
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unsigned int data_lane_shift:2;
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unsigned int data_lane_shift:3;
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unsigned int clk_pol:1;
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unsigned int hs_pol:1;
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unsigned int vs_pol:1;
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