drm/panel: Add ABT Y030XX067A 3.0" 320x480 panel
Add support for the ShenZhen Asia Better Technology Ltd. Y030XX067A 3.0" 320x480 IPS panel. This panel can be found in the YLM RG-280M, RG-300 and RG-99 handheld gaming consoles. While being 320x480, it is actually a horizontal 4:3 panel with non-square pixels. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Christophe Branchereau <cbranchereau@gmail.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20201101093150.8071-5-paul@crapouillou.net
This commit is contained in:
Paul Cercueil
parent
63ee07d5a8
commit
7467389bda
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@ -8,6 +8,15 @@ config DRM_PANEL
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menu "Display Panels"
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depends on DRM && DRM_PANEL
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config DRM_PANEL_ABT_Y030XX067A
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tristate "ABT Y030XX067A 320x480 LCD panel"
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depends on OF && SPI
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select REGMAP_SPI
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help
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Say Y here to enable support for the Asia Better Technology Ltd.
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Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
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and RG-99 handheld gaming consoles.
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config DRM_PANEL_ARM_VERSATILE
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tristate "ARM Versatile panel driver"
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depends on OF
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_DRM_PANEL_ABT_Y030XX067A) += panel-abt-y030xx067a.o
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obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
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obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596) += panel-asus-z00t-tm5p5-n35596.o
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obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
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@ -0,0 +1,363 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Asia Better Technology Ltd. Y030XX067A IPS LCD panel driver
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*
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* Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
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* Copyright (C) 2020, Christophe Branchereau <cbranchereau@gmail.com>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/media-bus-format.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#define REG00_VBRT_CTRL(val) (val)
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#define REG01_COM_DC(val) (val)
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#define REG02_DA_CONTRAST(val) (val)
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#define REG02_VESA_SEL(val) ((val) << 5)
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#define REG02_COMDC_SW BIT(7)
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#define REG03_VPOSITION(val) (val)
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#define REG03_BSMOUNT BIT(5)
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#define REG03_COMTST BIT(6)
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#define REG03_HPOSITION1 BIT(7)
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#define REG04_HPOSITION1(val) (val)
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#define REG05_CLIP BIT(0)
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#define REG05_NVM_VREFRESH BIT(1)
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#define REG05_SLFR BIT(2)
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#define REG05_SLBRCHARGE(val) ((val) << 3)
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#define REG05_PRECHARGE_LEVEL(val) ((val) << 6)
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#define REG06_TEST5 BIT(0)
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#define REG06_SLDWN BIT(1)
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#define REG06_SLRGT BIT(2)
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#define REG06_TEST2 BIT(3)
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#define REG06_XPSAVE BIT(4)
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#define REG06_GAMMA_SEL(val) ((val) << 5)
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#define REG06_NT BIT(7)
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#define REG07_TEST1 BIT(0)
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#define REG07_HDVD_POL BIT(1)
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#define REG07_CK_POL BIT(2)
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#define REG07_TEST3 BIT(3)
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#define REG07_TEST4 BIT(4)
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#define REG07_480_LINEMASK BIT(5)
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#define REG07_AMPTST(val) ((val) << 6)
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#define REG08_SLHRC(val) (val)
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#define REG08_CLOCK_DIV(val) ((val) << 2)
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#define REG08_PANEL(val) ((val) << 5)
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#define REG09_SUB_BRIGHT_R(val) (val)
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#define REG09_NW_NB BIT(6)
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#define REG09_IPCON BIT(7)
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#define REG0A_SUB_BRIGHT_B(val) (val)
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#define REG0A_PAIR BIT(6)
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#define REG0A_DE_SEL BIT(7)
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#define REG0B_MBK_POSITION(val) (val)
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#define REG0B_HD_FREERUN BIT(4)
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#define REG0B_VD_FREERUN BIT(5)
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#define REG0B_YUV2BIN(val) ((val) << 6)
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#define REG0C_CONTRAST_R(val) (val)
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#define REG0C_DOUBLEREAD BIT(7)
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#define REG0D_CONTRAST_G(val) (val)
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#define REG0D_RGB_YUV BIT(7)
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#define REG0E_CONTRAST_B(val) (val)
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#define REG0E_PIXELCOLORDRIVE BIT(7)
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#define REG0F_ASPECT BIT(0)
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#define REG0F_OVERSCAN(val) ((val) << 1)
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#define REG0F_FRAMEWIDTH(val) ((val) << 3)
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#define REG10_BRIGHT(val) (val)
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#define REG11_SIG_GAIN(val) (val)
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#define REG11_SIGC_CNTL BIT(6)
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#define REG11_SIGC_POL BIT(7)
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#define REG12_COLOR(val) (val)
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#define REG12_PWCKSEL(val) ((val) << 6)
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#define REG13_4096LEVEL_CNTL(val) (val)
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#define REG13_SL4096(val) ((val) << 4)
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#define REG13_LIMITER_CONTROL BIT(7)
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#define REG14_PANEL_TEST(val) (val)
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#define REG15_NVM_LINK0 BIT(0)
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#define REG15_NVM_LINK1 BIT(1)
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#define REG15_NVM_LINK2 BIT(2)
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#define REG15_NVM_LINK3 BIT(3)
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#define REG15_NVM_LINK4 BIT(4)
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#define REG15_NVM_LINK5 BIT(5)
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#define REG15_NVM_LINK6 BIT(6)
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#define REG15_NVM_LINK7 BIT(7)
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struct y030xx067a_info {
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const struct drm_display_mode *display_modes;
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unsigned int num_modes;
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u16 width_mm, height_mm;
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u32 bus_format, bus_flags;
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};
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struct y030xx067a {
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struct drm_panel panel;
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struct spi_device *spi;
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struct regmap *map;
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const struct y030xx067a_info *panel_info;
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struct regulator *supply;
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struct gpio_desc *reset_gpio;
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};
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static inline struct y030xx067a *to_y030xx067a(struct drm_panel *panel)
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{
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return container_of(panel, struct y030xx067a, panel);
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}
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static const struct reg_sequence y030xx067a_init_sequence[] = {
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{ 0x00, REG00_VBRT_CTRL(0x7f) },
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{ 0x01, REG01_COM_DC(0x3c) },
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{ 0x02, REG02_VESA_SEL(0x3) | REG02_DA_CONTRAST(0x1f) },
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{ 0x03, REG03_VPOSITION(0x0a) },
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{ 0x04, REG04_HPOSITION1(0xd2) },
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{ 0x05, REG05_CLIP | REG05_NVM_VREFRESH | REG05_SLBRCHARGE(0x2) },
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{ 0x06, REG06_XPSAVE | REG06_NT },
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{ 0x07, 0 },
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{ 0x08, REG08_PANEL(0x1) | REG08_CLOCK_DIV(0x2) },
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{ 0x09, REG09_SUB_BRIGHT_R(0x20) },
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{ 0x0a, REG0A_SUB_BRIGHT_B(0x20) },
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{ 0x0b, REG0B_HD_FREERUN | REG0B_VD_FREERUN },
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{ 0x0c, REG0C_CONTRAST_R(0x10) },
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{ 0x0d, REG0D_CONTRAST_G(0x10) },
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{ 0x0e, REG0E_CONTRAST_B(0x10) },
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{ 0x0f, 0 },
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{ 0x10, REG10_BRIGHT(0x7f) },
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{ 0x11, REG11_SIGC_CNTL | REG11_SIG_GAIN(0x3f) },
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{ 0x12, REG12_COLOR(0x20) | REG12_PWCKSEL(0x1) },
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{ 0x13, REG13_4096LEVEL_CNTL(0x8) },
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{ 0x14, 0 },
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{ 0x15, 0 },
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};
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static int y030xx067a_prepare(struct drm_panel *panel)
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{
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struct y030xx067a *priv = to_y030xx067a(panel);
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struct device *dev = &priv->spi->dev;
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int err;
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err = regulator_enable(priv->supply);
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if (err) {
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dev_err(dev, "Failed to enable power supply: %d\n", err);
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return err;
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}
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/* Reset the chip */
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gpiod_set_value_cansleep(priv->reset_gpio, 1);
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usleep_range(1000, 20000);
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gpiod_set_value_cansleep(priv->reset_gpio, 0);
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usleep_range(1000, 20000);
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err = regmap_multi_reg_write(priv->map, y030xx067a_init_sequence,
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ARRAY_SIZE(y030xx067a_init_sequence));
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if (err) {
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dev_err(dev, "Failed to init registers: %d\n", err);
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goto err_disable_regulator;
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}
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msleep(120);
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return 0;
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err_disable_regulator:
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regulator_disable(priv->supply);
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return err;
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}
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static int y030xx067a_unprepare(struct drm_panel *panel)
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{
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struct y030xx067a *priv = to_y030xx067a(panel);
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gpiod_set_value_cansleep(priv->reset_gpio, 1);
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regulator_disable(priv->supply);
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return 0;
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}
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static int y030xx067a_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct y030xx067a *priv = to_y030xx067a(panel);
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const struct y030xx067a_info *panel_info = priv->panel_info;
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struct drm_display_mode *mode;
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unsigned int i;
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for (i = 0; i < panel_info->num_modes; i++) {
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mode = drm_mode_duplicate(connector->dev,
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&panel_info->display_modes[i]);
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if (!mode)
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return -ENOMEM;
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drm_mode_set_name(mode);
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mode->type = DRM_MODE_TYPE_DRIVER;
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if (panel_info->num_modes == 1)
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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}
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connector->display_info.bpc = 8;
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connector->display_info.width_mm = panel_info->width_mm;
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connector->display_info.height_mm = panel_info->height_mm;
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drm_display_info_set_bus_formats(&connector->display_info,
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&panel_info->bus_format, 1);
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connector->display_info.bus_flags = panel_info->bus_flags;
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return panel_info->num_modes;
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}
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static const struct drm_panel_funcs y030xx067a_funcs = {
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.prepare = y030xx067a_prepare,
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.unprepare = y030xx067a_unprepare,
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.get_modes = y030xx067a_get_modes,
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};
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static const struct regmap_config y030xx067a_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 0x15,
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};
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static int y030xx067a_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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struct y030xx067a *priv;
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int err;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->spi = spi;
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spi_set_drvdata(spi, priv);
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priv->map = devm_regmap_init_spi(spi, &y030xx067a_regmap_config);
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if (IS_ERR(priv->map)) {
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dev_err(dev, "Unable to init regmap\n");
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return PTR_ERR(priv->map);
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}
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priv->panel_info = of_device_get_match_data(dev);
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if (!priv->panel_info)
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return -EINVAL;
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priv->supply = devm_regulator_get(dev, "power");
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if (IS_ERR(priv->supply)) {
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dev_err(dev, "Failed to get power supply\n");
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return PTR_ERR(priv->supply);
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}
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priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->reset_gpio)) {
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dev_err(dev, "Failed to get reset GPIO\n");
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return PTR_ERR(priv->reset_gpio);
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}
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drm_panel_init(&priv->panel, dev, &y030xx067a_funcs,
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DRM_MODE_CONNECTOR_DPI);
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err = drm_panel_of_backlight(&priv->panel);
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if (err)
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return err;
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drm_panel_add(&priv->panel);
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return 0;
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}
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static int y030xx067a_remove(struct spi_device *spi)
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{
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struct y030xx067a *priv = spi_get_drvdata(spi);
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drm_panel_remove(&priv->panel);
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drm_panel_disable(&priv->panel);
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drm_panel_unprepare(&priv->panel);
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return 0;
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}
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static const struct drm_display_mode y030xx067a_modes[] = {
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{ /* 60 Hz */
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.clock = 14400,
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.hdisplay = 320,
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.hsync_start = 320 + 10,
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.hsync_end = 320 + 10 + 37,
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.htotal = 320 + 10 + 37 + 33,
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.vdisplay = 480,
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.vsync_start = 480 + 84,
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.vsync_end = 480 + 84 + 20,
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.vtotal = 480 + 84 + 20 + 16,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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},
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{ /* 50 Hz */
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.clock = 12000,
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.hdisplay = 320,
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.hsync_start = 320 + 10,
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.hsync_end = 320 + 10 + 37,
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.htotal = 320 + 10 + 37 + 33,
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.vdisplay = 480,
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.vsync_start = 480 + 84,
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.vsync_end = 480 + 84 + 20,
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.vtotal = 480 + 84 + 20 + 16,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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},
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};
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static const struct y030xx067a_info y030xx067a_info = {
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.display_modes = y030xx067a_modes,
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.num_modes = ARRAY_SIZE(y030xx067a_modes),
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.width_mm = 69,
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.height_mm = 51,
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.bus_format = MEDIA_BUS_FMT_RGB888_3X8_DELTA,
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.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_DE_LOW,
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};
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static const struct of_device_id y030xx067a_of_match[] = {
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{ .compatible = "abt,y030xx067a", .data = &y030xx067a_info },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, y030xx067a_of_match);
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static struct spi_driver y030xx067a_driver = {
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.driver = {
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.name = "abt-y030xx067a",
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.of_match_table = y030xx067a_of_match,
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},
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.probe = y030xx067a_probe,
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.remove = y030xx067a_remove,
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};
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module_spi_driver(y030xx067a_driver);
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_AUTHOR("Christophe Branchereau <cbranchereau@gmail.com>");
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MODULE_LICENSE("GPL v2");
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