UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

clk: ingenic/jz4725b: Fix incorrect dividers for main clocks 

The main clocks (cclk, hclk, pclk, mclk, ipu) were using
incorrect dividers, and thus reported an incorrect rate.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Paul Cercueil 2019-05-02 23:25:01 +02:00 committed by Stephen Boyd
parent 44b06a76ad
commit 74054c413a
1 changed files with 24 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/clk/ingenic/jz4725b-cgu.c
View File

@ -33,6 +33,10 @@ static const s8 pll_od_encoding[4] = {
0x0, 0x1, -1, 0x3,
};
static const u8 jz4725b_cgu_cpccr_div_table[] = {
1, 2, 3, 4, 6, 8,
};
static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
/* External clocks */
@ -72,31 +76,46 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
[JZ4725B_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
},
},
[JZ4725B_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
},
},
[JZ4725B_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
},
},
[JZ4725B_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
},
},
[JZ4725B_CLK_IPU] = {
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
.div = {
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR, 13 },
},