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Merge tag 'hi6220-dt-for-4.8-2' of git://github.com/hisilicon/linux-hisi into next/late 

Merge "ARM64: DT: Hisilicon Hi6220 updates for 4.8" from Wei Xu:

- Add pl031 rtc0 and rtc1 support for hi6220 SoC

* tag 'hi6220-dt-for-4.8-2' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi6220: Add pl031 RTC support
  clk: hi6220: Add RTC clock for pl031
This commit is contained in:
Arnd Bergmann 2016-07-14 15:57:02 +02:00
parent 77938a9b4c 810bd15fe0
commit 73dd5c5bb0
3 changed files with 21 additions and 2 deletions
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16
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -336,6 +336,22 @@
clock-names = "timer1", "timer2", "apb_pclk";
};
rtc0: rtc@f8003000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0xf8003000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
clock-names = "apb_pclk";
};
rtc1: rtc@f8004000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0xf8004000 0x0 0x1000>;
interrupts = <0 8 4>;
clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
clock-names = "apb_pclk";
};
pmx0: pinmux@f7010000 {
compatible = "pinctrl-single";
reg = <0x0 0xf7010000 0x0 0x27c>;

2
drivers/clk/hisilicon/clk-hi6220.c
View File

@ -68,6 +68,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
{ HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
{ HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
{ HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
{ HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
{ HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
};
static void __init hi6220_clk_ao_init(struct device_node *np)

5
include/dt-bindings/clock/hi6220-clock.h
View File

@ -55,8 +55,9 @@
#define HI6220_TIMER7_PCLK 34
#define HI6220_TIMER8_PCLK 35
#define HI6220_UART0_PCLK 36
#define HI6220_AO_NR_CLKS 37
#define HI6220_RTC0_PCLK 37
#define HI6220_RTC1_PCLK 38
#define HI6220_AO_NR_CLKS 39
/* clk in Hi6220 systrl */
/* gate clock */