drm/mediatek: Adjust to the alphabetic order for mediatek-drm
Adjust to the alphabetic order for the define, function, struct and array in mediatek-drm driver Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
jason-jh.lin
Chun-Kuang Hu
parent
aa0c31554e
commit
73d3724745
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@ -20,42 +20,40 @@
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_crtc.h"
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#define DISP_REG_OD_EN 0x0000
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#define DISP_REG_OD_CFG 0x0020
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#define DISP_REG_OD_SIZE 0x0030
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#define DISP_REG_DITHER_5 0x0114
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#define DISP_REG_DITHER_7 0x011c
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#define DISP_REG_DITHER_15 0x013c
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#define DISP_REG_DITHER_16 0x0140
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#define DISP_REG_UFO_START 0x0000
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#define DISP_REG_DITHER_EN 0x0000
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#define DITHER_EN BIT(0)
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#define DISP_REG_DITHER_CFG 0x0020
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#define DITHER_RELAY_MODE BIT(0)
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#define DITHER_ENGINE_EN BIT(1)
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#define DISP_REG_DITHER_SIZE 0x0030
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#define OD_RELAYMODE BIT(0)
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#define UFO_BYPASS BIT(2)
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#define DISP_DITHERING BIT(2)
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#define DISP_REG_DITHER_SIZE 0x0030
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#define DISP_REG_DITHER_5 0x0114
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#define DISP_REG_DITHER_7 0x011c
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#define DISP_REG_DITHER_15 0x013c
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#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
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#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
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#define DITHER_NEW_BIT_MODE BIT(0)
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#define DISP_REG_DITHER_16 0x0140
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#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
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#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
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#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
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#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
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#define DISP_REG_OD_EN 0x0000
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#define DISP_REG_OD_CFG 0x0020
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#define OD_RELAYMODE BIT(0)
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#define DISP_REG_OD_SIZE 0x0030
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#define DISP_REG_POSTMASK_EN 0x0000
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#define POSTMASK_EN BIT(0)
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#define DISP_REG_POSTMASK_CFG 0x0020
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#define POSTMASK_RELAY_MODE BIT(0)
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#define DISP_REG_POSTMASK_SIZE 0x0030
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#define DISP_REG_UFO_START 0x0000
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#define UFO_BYPASS BIT(2)
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struct mtk_ddp_comp_dev {
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struct clk *clk;
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void __iomem *regs;
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@ -147,8 +145,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
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}
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}
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static void mtk_dither_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
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mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
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DISP_REG_DITHER_CFG);
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mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
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DITHER_ENGINE_EN, cmdq_pkt);
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}
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static void mtk_dither_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_dither_stop(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_dither_set(struct device *dev, unsigned int bpc,
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unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
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unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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@ -174,41 +199,6 @@ static void mtk_od_start(struct device *dev)
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writel(1, priv->regs + DISP_REG_OD_EN);
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}
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static void mtk_ufoe_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
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}
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static void mtk_dither_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
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DISP_REG_DITHER_SIZE);
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mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
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DISP_REG_DITHER_CFG);
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mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
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DITHER_ENGINE_EN, cmdq_pkt);
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}
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static void mtk_dither_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_dither_stop(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_postmask_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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@ -235,6 +225,13 @@ static void mtk_postmask_stop(struct device *dev)
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writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
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}
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static void mtk_ufoe_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
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}
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static const struct mtk_ddp_comp_funcs ddp_aal = {
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.clk_enable = mtk_aal_clk_enable,
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.clk_disable = mtk_aal_clk_disable,
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@ -337,23 +334,23 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
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};
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static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
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[MTK_DISP_OVL] = "ovl",
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[MTK_DISP_OVL_2L] = "ovl-2l",
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[MTK_DISP_RDMA] = "rdma",
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[MTK_DISP_WDMA] = "wdma",
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[MTK_DISP_COLOR] = "color",
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[MTK_DISP_CCORR] = "ccorr",
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[MTK_DISP_AAL] = "aal",
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[MTK_DISP_GAMMA] = "gamma",
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[MTK_DISP_BLS] = "bls",
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[MTK_DISP_CCORR] = "ccorr",
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[MTK_DISP_COLOR] = "color",
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[MTK_DISP_DITHER] = "dither",
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[MTK_DISP_UFOE] = "ufoe",
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[MTK_DSI] = "dsi",
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[MTK_DPI] = "dpi",
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[MTK_DISP_PWM] = "pwm",
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[MTK_DISP_GAMMA] = "gamma",
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[MTK_DISP_MUTEX] = "mutex",
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[MTK_DISP_OD] = "od",
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[MTK_DISP_BLS] = "bls",
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[MTK_DISP_OVL] = "ovl",
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[MTK_DISP_OVL_2L] = "ovl-2l",
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[MTK_DISP_POSTMASK] = "postmask",
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[MTK_DISP_PWM] = "pwm",
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[MTK_DISP_RDMA] = "rdma",
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[MTK_DISP_UFOE] = "ufoe",
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[MTK_DISP_WDMA] = "wdma",
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[MTK_DPI] = "dpi",
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[MTK_DSI] = "dsi",
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};
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struct mtk_ddp_comp_match {
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@ -511,12 +508,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
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type == MTK_DISP_CCORR ||
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type == MTK_DISP_COLOR ||
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type == MTK_DISP_GAMMA ||
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type == MTK_DPI ||
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type == MTK_DSI ||
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type == MTK_DISP_OVL ||
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type == MTK_DISP_OVL_2L ||
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type == MTK_DISP_PWM ||
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type == MTK_DISP_RDMA)
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type == MTK_DISP_RDMA ||
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type == MTK_DPI ||
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type == MTK_DSI)
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return 0;
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priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
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@ -18,23 +18,23 @@ struct mtk_plane_state;
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struct drm_crtc_state;
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enum mtk_ddp_comp_type {
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MTK_DISP_OVL,
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MTK_DISP_OVL_2L,
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MTK_DISP_RDMA,
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MTK_DISP_WDMA,
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MTK_DISP_COLOR,
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MTK_DISP_CCORR,
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MTK_DISP_DITHER,
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MTK_DISP_AAL,
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MTK_DISP_BLS,
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MTK_DISP_CCORR,
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MTK_DISP_COLOR,
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MTK_DISP_DITHER,
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MTK_DISP_GAMMA,
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MTK_DISP_UFOE,
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MTK_DSI,
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MTK_DPI,
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MTK_DISP_POSTMASK,
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MTK_DISP_PWM,
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MTK_DISP_MUTEX,
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MTK_DISP_OD,
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MTK_DISP_BLS,
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MTK_DISP_OVL,
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MTK_DISP_OVL_2L,
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MTK_DISP_POSTMASK,
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MTK_DISP_PWM,
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MTK_DISP_RDMA,
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MTK_DISP_UFOE,
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MTK_DISP_WDMA,
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MTK_DPI,
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MTK_DSI,
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MTK_DDP_COMP_TYPE_MAX,
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};
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@ -423,32 +423,14 @@ static const struct component_master_ops mtk_drm_ops = {
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};
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static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
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{ .compatible = "mediatek,mt2701-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8167-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8173-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8183-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8183-disp-ovl-2l",
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.data = (void *)MTK_DISP_OVL_2L },
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{ .compatible = "mediatek,mt8192-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8192-disp-ovl-2l",
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.data = (void *)MTK_DISP_OVL_2L },
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{ .compatible = "mediatek,mt2701-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8167-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8173-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8183-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8192-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8173-disp-wdma",
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.data = (void *)MTK_DISP_WDMA },
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{ .compatible = "mediatek,mt8167-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8173-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8183-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8192-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8167-disp-ccorr",
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.data = (void *)MTK_DISP_CCORR },
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{ .compatible = "mediatek,mt8183-disp-ccorr",
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@ -461,40 +443,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
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.data = (void *)MTK_DISP_COLOR },
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{ .compatible = "mediatek,mt8173-disp-color",
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.data = (void *)MTK_DISP_COLOR },
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{ .compatible = "mediatek,mt8167-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8173-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8183-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8192-disp-aal",
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.data = (void *)MTK_DISP_AAL},
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{ .compatible = "mediatek,mt8167-disp-dither",
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.data = (void *)MTK_DISP_DITHER },
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{ .compatible = "mediatek,mt8183-disp-dither",
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.data = (void *)MTK_DISP_DITHER },
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{ .compatible = "mediatek,mt8167-disp-gamma",
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.data = (void *)MTK_DISP_GAMMA, },
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{ .compatible = "mediatek,mt8173-disp-gamma",
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.data = (void *)MTK_DISP_GAMMA, },
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{ .compatible = "mediatek,mt8183-disp-gamma",
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.data = (void *)MTK_DISP_GAMMA, },
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{ .compatible = "mediatek,mt8167-disp-dither",
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.data = (void *)MTK_DISP_DITHER },
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{ .compatible = "mediatek,mt8183-disp-dither",
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.data = (void *)MTK_DISP_DITHER },
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{ .compatible = "mediatek,mt8173-disp-ufoe",
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.data = (void *)MTK_DISP_UFOE },
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{ .compatible = "mediatek,mt2701-dsi",
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.data = (void *)MTK_DSI },
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{ .compatible = "mediatek,mt8167-dsi",
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.data = (void *)MTK_DSI },
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{ .compatible = "mediatek,mt8173-dsi",
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.data = (void *)MTK_DSI },
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{ .compatible = "mediatek,mt8183-dsi",
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.data = (void *)MTK_DSI },
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{ .compatible = "mediatek,mt2701-dpi",
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.data = (void *)MTK_DPI },
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{ .compatible = "mediatek,mt8173-dpi",
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.data = (void *)MTK_DPI },
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{ .compatible = "mediatek,mt8183-dpi",
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.data = (void *)MTK_DPI },
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{ .compatible = "mediatek,mt2701-disp-mutex",
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.data = (void *)MTK_DISP_MUTEX },
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{ .compatible = "mediatek,mt2712-disp-mutex",
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@ -507,16 +465,58 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
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.data = (void *)MTK_DISP_MUTEX },
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{ .compatible = "mediatek,mt8192-disp-mutex",
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.data = (void *)MTK_DISP_MUTEX },
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{ .compatible = "mediatek,mt8173-disp-od",
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.data = (void *)MTK_DISP_OD },
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{ .compatible = "mediatek,mt2701-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8167-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8173-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8183-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8192-disp-ovl",
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.data = (void *)MTK_DISP_OVL },
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{ .compatible = "mediatek,mt8183-disp-ovl-2l",
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.data = (void *)MTK_DISP_OVL_2L },
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{ .compatible = "mediatek,mt8192-disp-ovl-2l",
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.data = (void *)MTK_DISP_OVL_2L },
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{ .compatible = "mediatek,mt8192-disp-postmask",
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.data = (void *)MTK_DISP_POSTMASK },
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{ .compatible = "mediatek,mt2701-disp-pwm",
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.data = (void *)MTK_DISP_BLS },
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{ .compatible = "mediatek,mt8167-disp-pwm",
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.data = (void *)MTK_DISP_PWM },
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{ .compatible = "mediatek,mt8173-disp-pwm",
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.data = (void *)MTK_DISP_PWM },
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{ .compatible = "mediatek,mt8173-disp-od",
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.data = (void *)MTK_DISP_OD },
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{ .compatible = "mediatek,mt8192-disp-postmask",
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.data = (void *)MTK_DISP_POSTMASK },
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{ .compatible = "mediatek,mt2701-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8167-disp-rdma",
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.data = (void *)MTK_DISP_RDMA },
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{ .compatible = "mediatek,mt8173-disp-rdma",
|
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.data = (void *)MTK_DISP_RDMA },
|
||||
{ .compatible = "mediatek,mt8183-disp-rdma",
|
||||
.data = (void *)MTK_DISP_RDMA },
|
||||
{ .compatible = "mediatek,mt8192-disp-rdma",
|
||||
.data = (void *)MTK_DISP_RDMA },
|
||||
{ .compatible = "mediatek,mt8173-disp-ufoe",
|
||||
.data = (void *)MTK_DISP_UFOE },
|
||||
{ .compatible = "mediatek,mt8173-disp-wdma",
|
||||
.data = (void *)MTK_DISP_WDMA },
|
||||
{ .compatible = "mediatek,mt2701-dpi",
|
||||
.data = (void *)MTK_DPI },
|
||||
{ .compatible = "mediatek,mt8167-dsi",
|
||||
.data = (void *)MTK_DSI },
|
||||
{ .compatible = "mediatek,mt8173-dpi",
|
||||
.data = (void *)MTK_DPI },
|
||||
{ .compatible = "mediatek,mt8183-dpi",
|
||||
.data = (void *)MTK_DPI },
|
||||
{ .compatible = "mediatek,mt2701-dsi",
|
||||
.data = (void *)MTK_DSI },
|
||||
{ .compatible = "mediatek,mt8173-dsi",
|
||||
.data = (void *)MTK_DSI },
|
||||
{ .compatible = "mediatek,mt8183-dsi",
|
||||
.data = (void *)MTK_DSI },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -610,8 +610,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
|
|||
comp_type == MTK_DISP_OVL ||
|
||||
comp_type == MTK_DISP_OVL_2L ||
|
||||
comp_type == MTK_DISP_RDMA ||
|
||||
comp_type == MTK_DSI ||
|
||||
comp_type == MTK_DPI) {
|
||||
comp_type == MTK_DPI ||
|
||||
comp_type == MTK_DSI) {
|
||||
dev_info(dev, "Adding component match for %pOF\n",
|
||||
node);
|
||||
drm_of_component_match_add(dev, &match, compare_of,
|
||||
|
|
|
|||
Loading…
Reference in New Issue