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drm/i915/ats-m: Add thread execution tuning setting 

On client DG2 platforms, optimal performance is achieved with the
hardware's default "age based" thread execution setting.  However on
ATS-M, switching this to "round robin after dependencies" provides
better performance.  We'll add a new "tuning" feature flag to the ATS-M
device info to enable/disable this setting.

Bspec: 68331
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220826212718.409948-1-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper 2022-08-26 14:27:18 -07:00
parent d9927abb45
commit 73c7a8a871
4 changed files with 13 additions and 0 deletions
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2
drivers/gpu/drm/i915/gt/intel_gt_regs.h
View File

@ -1110,6 +1110,8 @@
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9) #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7) #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)

9
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -2700,6 +2700,15 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
0 /* write-only, so skip validation */, 0 /* write-only, so skip validation */,
true); true);
} }
/*
* This tuning setting proves beneficial only on ATS-M designs; the
* default "age based" setting is optimal on regular DG2 and other
* platforms.
*/
if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
wa_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
THREAD_EX_ARB_MODE_RR_AFTER_DEP);
} }
/* /*

1
drivers/gpu/drm/i915/i915_pci.c
View File

@ -1083,6 +1083,7 @@ static const struct intel_device_info ats_m_info = {
DG2_FEATURES, DG2_FEATURES,
.display = { 0 }, .display = { 0 },
.require_force_probe = 1, .require_force_probe = 1,
.tuning_thread_rr_after_dep = 1,
}; };
#define XE_HPC_FEATURES \ #define XE_HPC_FEATURES \

1
drivers/gpu/drm/i915/intel_device_info.h
View File

@ -172,6 +172,7 @@ enum intel_ppgtt_type {
func(has_runtime_pm); \ func(has_runtime_pm); \
func(has_snoop); \ func(has_snoop); \
func(has_coherent_ggtt); \ func(has_coherent_ggtt); \
func(tuning_thread_rr_after_dep); \
func(unfenced_needs_alignment); \ func(unfenced_needs_alignment); \
func(hws_needs_physical); func(hws_needs_physical);