ASoC: SOF: amd: Add IPC support for ACP IP block
Add IPC module for generic ACP block and exposed ops callback for to synchronize SOF IPC message between host and DSP Signed-off-by: Balakishore Pati <Balakishore.pati@amd.com> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Reviewed-by: Bard Liao <bard.liao@intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20211117093734.17407-5-daniel.baluta@oss.nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ajit Kumar Pandey
Mark Brown
parent
7e51a9e38a
commit
738a2b5e2c
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@ -4,7 +4,7 @@
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#
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# Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
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snd-sof-amd-acp-objs := acp.o acp-loader.o
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snd-sof-amd-acp-objs := acp.o acp-loader.o acp-ipc.o
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snd-sof-amd-renoir-objs := renoir.o
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obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o
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@ -53,6 +53,8 @@
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/* Registers from ACP_INTR block */
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#define ACP_DSP_SW_INTR_CNTL 0x1814
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#define ACP_DSP_SW_INTR_STAT 0x1818
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#define ACP_SW_INTR_TRIG 0x181C
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#define ACP_ERROR_STATUS 0x18C4
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/* Registers from ACP_SHA block */
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@ -0,0 +1,187 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2021 Advanced Micro Devices, Inc.
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//
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// Authors: Balakishore Pati <Balakishore.pati@amd.com>
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// Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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/* ACP-specific SOF IPC code */
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#include <linux/module.h>
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#include "../ops.h"
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#include "acp.h"
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#include "acp-dsp-offset.h"
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void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
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{
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memcpy_to_scratch(sdev, offset, message, bytes);
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}
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EXPORT_SYMBOL_NS(acp_mailbox_write, SND_SOC_SOF_AMD_COMMON);
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void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
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{
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memcpy_from_scratch(sdev, offset, message, bytes);
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}
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EXPORT_SYMBOL_NS(acp_mailbox_read, SND_SOC_SOF_AMD_COMMON);
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static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
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{
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struct snd_sof_dev *sdev = adata->dev;
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u32 swintr_trigger;
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swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG);
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swintr_trigger |= 0x01;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG, swintr_trigger);
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}
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static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
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{
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unsigned int host_msg = offsetof(struct scratch_ipc_conf, sof_host_msg_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
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}
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static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
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{
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unsigned int dsp_msg = offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
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}
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static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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unsigned int dsp_ack = offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
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}
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int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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unsigned int offset = offsetof(struct scratch_ipc_conf, sof_in_box);
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acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
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acp_ipc_host_msg_set(sdev);
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/* Trigger host to dsp interrupt for the msg */
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acpbus_trigger_host_to_dsp_swintr(adata);
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON);
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static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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struct sof_ipc_cmd_hdr *hdr;
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unsigned int offset = offsetof(struct scratch_ipc_conf, sof_in_box);
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int ret = 0;
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/*
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* Sometimes, there is unexpected reply ipc arriving. The reply
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* ipc belongs to none of the ipcs sent from driver.
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* In this case, the driver must ignore the ipc.
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*/
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
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return;
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}
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hdr = msg->msg_data;
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if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
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hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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/*
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* memory windows are powered off before sending IPC reply,
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* so we can't read the mailbox for CTX_SAVE and PM_GATE
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* replies.
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*/
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reply.error = 0;
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reply.hdr.cmd = SOF_IPC_GLB_REPLY;
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reply.hdr.size = sizeof(reply);
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memcpy(msg->reply_data, &reply, sizeof(reply));
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goto out;
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}
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/* get IPC reply from DSP in the mailbox */
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acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply correct size ? */
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if (reply.hdr.size != msg->reply_size &&
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!(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) {
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dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
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}
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out:
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msg->reply_error = ret;
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}
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irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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unsigned int dsp_msg_write = offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
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unsigned int dsp_ack_write = offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
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bool ipc_irq = false;
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int dsp_msg, dsp_ack;
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dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
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if (dsp_msg) {
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snd_sof_ipc_msgs_rx(sdev);
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acp_dsp_ipc_host_done(sdev);
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ipc_irq = true;
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}
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dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
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if (dsp_ack) {
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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acp_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, 0);
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/* set the done bit */
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acp_dsp_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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ipc_irq = true;
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}
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if (!ipc_irq)
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dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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void *p, size_t sz)
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{
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unsigned int offset = offsetof(struct scratch_ipc_conf, sof_out_box);
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if (!substream || !sdev->stream_box.size)
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acp_mailbox_read(sdev, offset, p, sz);
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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const struct sof_ipc_pcm_params_reply *reply)
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{
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/* TODO: Implement stream hw params to validate stream offset */
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_pcm_params, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return ACP_SCRATCH_MEMORY_ADDRESS;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, SND_SOC_SOF_AMD_COMMON);
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MODULE_DESCRIPTION("AMD ACP sof-ipc driver");
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@ -233,6 +233,34 @@ static int acp_memory_init(struct snd_sof_dev *sdev)
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return 0;
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}
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static irqreturn_t acp_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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unsigned int val;
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT);
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if (val & ACP_DSP_TO_HOST_IRQ) {
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sof_ops(sdev)->irq_thread(irq, sdev);
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val |= ACP_DSP_TO_HOST_IRQ;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT, val);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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};
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static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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{
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struct snd_sof_dev *sdev = dev_id;
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unsigned int val;
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT);
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if (val)
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return IRQ_WAKE_THREAD;
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return IRQ_NONE;
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}
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static int acp_power_on(struct snd_sof_dev *sdev)
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{
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unsigned int val;
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@ -318,9 +346,20 @@ int amd_sof_acp_probe(struct snd_sof_dev *sdev)
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sdev->pdata->hw_pdata = adata;
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ret = acp_init(sdev);
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if (ret < 0)
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sdev->ipc_irq = pci->irq;
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ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
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IRQF_SHARED, "AudioDSP", sdev);
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if (ret < 0) {
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dev_err(sdev->dev, "failed to register IRQ %d\n",
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sdev->ipc_irq);
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return ret;
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}
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ret = acp_init(sdev);
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if (ret < 0) {
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free_irq(sdev->ipc_irq, sdev);
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return ret;
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}
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acp_memory_init(sdev);
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@ -330,6 +369,9 @@ EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);
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int amd_sof_acp_remove(struct snd_sof_dev *sdev)
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{
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if (sdev->ipc_irq)
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free_irq(sdev->ipc_irq, sdev);
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return acp_reset(sdev);
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}
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EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);
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@ -48,6 +48,8 @@
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#define ACP_DATA_RAM_BASE_ADDRESS 0x01000000
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#define ACP_DRAM_PAGE_COUNT 128
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#define ACP_DSP_TO_HOST_IRQ 0x04
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struct acp_atu_grp_pte {
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u32 low;
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u32 high;
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@ -150,5 +152,18 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t
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int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
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u32 offset, void *dest, size_t size);
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/* IPC callbacks */
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irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
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int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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void *p, size_t sz);
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int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
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int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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const struct sof_ipc_pcm_params_reply *reply);
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void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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extern const struct snd_sof_dsp_ops sof_renoir_ops;
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#endif
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@ -41,6 +41,14 @@ const struct snd_sof_dsp_ops sof_renoir_ops = {
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/* DSP core boot */
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.run = acp_sof_dsp_run,
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/*IPC */
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.send_msg = acp_sof_ipc_send_msg,
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.ipc_msg_data = acp_sof_ipc_msg_data,
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.ipc_pcm_params = acp_sof_ipc_pcm_params,
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.get_mailbox_offset = acp_sof_ipc_get_mailbox_offset,
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.irq_thread = acp_sof_ipc_irq_thread,
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.fw_ready = sof_fw_ready,
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};
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EXPORT_SYMBOL(sof_renoir_ops);
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