drm/armada: fix overlay when partially off-screen
Fix the start address calculation when overlay is partially off screen. fb->bits_per_pixel is not set for YUV formats, and is always zero, which led to the first component always starting at zero. Use drm_format_plane_cpp() instead. This also revealed a problem in that YUYV formats toggle the U/V data for odd pixel start address offsets. We try to rectify that by toggling the U/V swap, which for the most part works, but seemingly introduces a flicker for one scan frame of swapped U/V. However, these changes result in an overall improvement. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -166,7 +166,8 @@ armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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if (plane->fb != fb) {
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struct armada_gem_object *obj = drm_fb_obj(fb);
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uint32_t sy, su, sv;
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uint32_t addr[3], pixel_format;
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int i, num_planes, hsub;
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/*
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* Take a reference on the new framebuffer - we want to
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@ -188,24 +189,37 @@ armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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src_y = src.y1 >> 16;
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src_x = src.x1 >> 16;
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sy = obj->dev_addr + fb->offsets[0] + src_y * fb->pitches[0] +
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src_x * fb->bits_per_pixel / 8;
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su = obj->dev_addr + fb->offsets[1] + src_y * fb->pitches[1] +
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src_x;
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sv = obj->dev_addr + fb->offsets[2] + src_y * fb->pitches[2] +
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src_x;
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armada_reg_queue_set(dplane->vbl.regs, idx, sy,
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pixel_format = fb->pixel_format;
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hsub = drm_format_horz_chroma_subsampling(pixel_format);
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num_planes = drm_format_num_planes(pixel_format);
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/*
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* Annoyingly, shifting a YUYV-format image by one pixel
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* causes the U/V planes to toggle. Toggle the UV swap.
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* (Unfortunately, this causes momentary colour flickering.)
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*/
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if (src_x & (hsub - 1) && num_planes == 1)
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ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
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for (i = 0; i < num_planes; i++)
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addr[i] = obj->dev_addr + fb->offsets[i] +
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src_y * fb->pitches[i] +
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src_x * drm_format_plane_cpp(pixel_format, i);
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for (; i < ARRAY_SIZE(addr); i++)
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addr[i] = 0;
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
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LCD_SPU_DMA_START_ADDR_Y0);
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armada_reg_queue_set(dplane->vbl.regs, idx, su,
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
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LCD_SPU_DMA_START_ADDR_U0);
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armada_reg_queue_set(dplane->vbl.regs, idx, sv,
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
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LCD_SPU_DMA_START_ADDR_V0);
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armada_reg_queue_set(dplane->vbl.regs, idx, sy,
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
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LCD_SPU_DMA_START_ADDR_Y1);
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armada_reg_queue_set(dplane->vbl.regs, idx, su,
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
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LCD_SPU_DMA_START_ADDR_U1);
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armada_reg_queue_set(dplane->vbl.regs, idx, sv,
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armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
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LCD_SPU_DMA_START_ADDR_V1);
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val = fb->pitches[0] << 16 | fb->pitches[0];
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