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omap3: clock: Fixed dpll3_m2x2 rate calculation 

Current calculation does not take into account any changes to M2 divisor, and
thus when we change VDD2 OPP, dpll3_m2x2 rate does not change. Fixed by
re-routing dpll3_m2x2 parent to dpll3_m2.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo 2009-11-16 13:36:54 +00:00 committed by Tony Lindgren
parent 9346f48b26
commit 72f962fc7b
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-omap2/clock34xx.h
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@ -489,9 +489,9 @@ static struct clk core_ck = {
static struct clk dpll3_m2x2_ck = {
.name = "dpll3_m2x2_ck",
.ops = &clkops_null,
.parent = &dpll3_x2_ck,
.parent = &dpll3_m2_ck,
.clkdm_name = "dpll3_clkdm",
.recalc = &followparent_recalc,
.recalc = &omap3_clkoutx2_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */