Qualcomm ARM64 Updates for v5.3 Part 2
* Add SDM845 Cheza support * Add TSENS controller and thermal zones for QCS404 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdFaUdAAoJEFKiBbHx2RXVByQP/2pjLfvxvUEiimdDO6ZxsqhK DdcUQr+edWIg9pxZM8Q/oVLNJd+CGXdgG1X9EhPRL66rEDrcADWgxopFE0pQDLwn kRZ+nicUID+50Hr5QAG4+maeeh1xjLeondRsmnr1xUNJ0GTcdwj9G8Wua/AlBRhh wF6eBzAwVpwvbUWbXMo6OjFyPHnvM8Itsqp5oyGtoy+SoZiWrNYvkhP0rtEM9pmc SFk/zbfdYZCDfRdxI6W36gcBlqhBLKDgJ3zlgSoNFdQ3HRC+gI0RylWhEN9aXVK1 RTIjrmDcIXwqD0zAJnAgUUx2JpWsEpebZ83ZaFfkumfSZwheGmcpu/0D8RNh6b07 4WrdEnvkwpxH3QSsUL/fHvot5tq8lNu2xgIsDuq+eHZZD2l/VZWR6xsQ9FeiHwm+ pfKbL/vo46UjN4maJPG4aVCBxR30BFnohECHrnBHntBHQzfg0NVASbm+fPYzC80T PxY8XY3UdTs3I7VUS5uDD/GzQtiLd2C//0FeQj8AUOHttElYI2iO6YapXT3jvIic nLeBCIjPjXm0+LjUfeZJlw/PcuGkSLxcwGf9HouI1bEUq82HXnoy5vVODltvUZhj 0GsBc0NN198NuzdWGzu+2cRzukOAAB4aSNS3S5Xf1IMbHXG2vL16Z83WjZ8pp92I aEbeYtK34uFYdYZ3+tJD =gjue -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 Updates for v5.3 Part 2 * Add SDM845 Cheza support * Add TSENS controller and thermal zones for QCS404 * tag 'qcom-arm64-for-5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: qcs404: Add missing space for cooling-cells property arm64: dts: qcom: sdm845-cheza: add initial cheza dt arm64: dts: qcom: qcs404: Add thermal zones for each sensor arm64: dts: qcom: qcs404: Add tsens controller Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
72ce9b7cab
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@ -7,6 +7,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
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@ -6,6 +6,7 @@
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#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&intc>;
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@ -34,6 +35,7 @@
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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};
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CPU1: cpu@101 {
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@ -43,6 +45,7 @@
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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};
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CPU2: cpu@102 {
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@ -52,6 +55,7 @@
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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};
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CPU3: cpu@103 {
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@ -61,6 +65,7 @@
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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};
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L2_0: l2-cache {
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@ -251,6 +256,16 @@
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reg = <0x00060000 0x6000>;
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};
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qfprom: qfprom@a4000 {
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compatible = "qcom,qfprom";
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reg = <0x000a4000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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tsens_caldata: caldata@d0 {
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reg = <0x1f8 0x14>;
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};
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};
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rng: rng@e3000 {
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compatible = "qcom,prng-ee";
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reg = <0x000e3000 0x1000>;
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@ -258,6 +273,16 @@
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clock-names = "core";
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};
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tsens: thermal-sensor@4a9000 {
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compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
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reg = <0x004a9000 0x1000>, /* TM */
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<0x004a8000 0x1000>; /* SROT */
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nvmem-cells = <&tsens_caldata>;
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nvmem-cell-names = "calib";
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#qcom,sensors = <10>;
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#thermal-sensor-cells = <1>;
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};
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remoteproc_cdsp: remoteproc@b00000 {
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compatible = "qcom,qcs404-cdsp-pas";
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reg = <0x00b00000 0x4040>;
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@ -1043,4 +1068,251 @@
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#interrupt-cells = <2>;
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};
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};
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thermal-zones {
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aoss-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 0>;
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trips {
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aoss_alert0: trip-point@0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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q6-hvx-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 1>;
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trips {
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q6_hvx_alert0: trip-point@0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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lpass-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 2>;
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trips {
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lpass_alert0: trip-point@0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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wlan-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 3>;
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trips {
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wlan_alert0: trip-point@0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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cluster-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 4>;
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trips {
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cluster_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cluster_alert1: trip-point@1 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cluster_crit: cluster_crit {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cluster_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 5>;
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trips {
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cpu0_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu0_alert1: trip-point@1 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu0_crit: cpu_crit {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu0_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 6>;
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trips {
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cpu1_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu1_alert1: trip-point@1 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu1_crit: cpu_crit {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu1_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu2-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 7>;
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trips {
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cpu2_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu2_alert1: trip-point@1 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu2_crit: cpu_crit {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu2_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu3-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 8>;
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trips {
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cpu3_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu3_alert1: trip-point@1 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu3_crit: cpu_crit {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu3_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 9>;
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trips {
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gpu_alert0: trip-point@0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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};
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};
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@ -0,0 +1,238 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Cheza board device tree source
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*
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* Copyright 2018 Google LLC.
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*/
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/dts-v1/;
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#include "sdm845-cheza.dtsi"
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/ {
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model = "Google Cheza (rev1)";
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||||
compatible = "google,cheza-rev1", "qcom,sdm845";
|
||||
|
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/*
|
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* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
|
||||
*/
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||||
|
||||
/*
|
||||
* NOTE: Technically pp3500_a is not the exact same signal as
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* pp3500_a_vbob (there's a load switch between them and the EC can
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* control pp3500_a via "en_pp3300_a"), but from the AP's point of
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* view they are the same.
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*/
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pp3500_a:
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pp3500_a_vbob: pp3500-a-vbob-regulator {
|
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compatible = "regulator-fixed";
|
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regulator-name = "vreg_bob";
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|
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/*
|
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* Comes on automatically when pp5000_ldo comes on, which
|
||||
* comes on automatically when ppvar_sys comes on
|
||||
*/
|
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regulator-always-on;
|
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regulator-boot-on;
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regulator-min-microvolt = <3500000>;
|
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regulator-max-microvolt = <3500000>;
|
||||
|
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vin-supply = <&ppvar_sys>;
|
||||
};
|
||||
|
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pp3300_dx_edp: pp3300-dx-edp-regulator {
|
||||
/* Yes, it's really 3.5 despite the name of the signal */
|
||||
regulator-min-microvolt = <3500000>;
|
||||
regulator-max-microvolt = <3500000>;
|
||||
|
||||
vin-supply = <&pp3500_a>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
|
||||
|
||||
/*
|
||||
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
|
||||
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
|
||||
* prevents the system from booting.
|
||||
*/
|
||||
&src_pp3000_l19a {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
|
||||
&src_pp3300_l22a {
|
||||
/delete-property/regulator-boot-on;
|
||||
/delete-property/regulator-always-on;
|
||||
};
|
||||
|
||||
&src_pp3300_l28a {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
|
||||
&src_vreg_bob {
|
||||
regulator-min-microvolt = <3500000>;
|
||||
regulator-max-microvolt = <3500000>;
|
||||
vin-supply = <&pp3500_a_vbob>;
|
||||
};
|
||||
|
||||
/*
|
||||
* NON-REGULATOR OVERRIDES
|
||||
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
|
||||
*/
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
|
||||
&tlmm {
|
||||
gpio-line-names = "AP_SPI_FP_MISO",
|
||||
"AP_SPI_FP_MOSI",
|
||||
"AP_SPI_FP_CLK",
|
||||
"AP_SPI_FP_CS_L",
|
||||
"UART_AP_TX_DBG_RX",
|
||||
"UART_DBG_TX_AP_RX",
|
||||
"",
|
||||
"FP_RST_L",
|
||||
"FCAM_EN",
|
||||
"",
|
||||
"EDP_BRIJ_IRQ",
|
||||
"EC_IN_RW_ODL",
|
||||
"",
|
||||
"RCAM_MCLK",
|
||||
"FCAM_MCLK",
|
||||
"",
|
||||
"RCAM_EN",
|
||||
"CCI0_SDA",
|
||||
"CCI0_SCL",
|
||||
"CCI1_SDA",
|
||||
"CCI1_SCL",
|
||||
"FCAM_RST_L",
|
||||
"",
|
||||
"PEN_RST_L",
|
||||
"PEN_IRQ_L",
|
||||
"",
|
||||
"RCAM_VSYNC",
|
||||
"ESIM_MISO",
|
||||
"ESIM_MOSI",
|
||||
"ESIM_CLK",
|
||||
"ESIM_CS_L",
|
||||
"AP_PEN_1V8_SDA",
|
||||
"AP_PEN_1V8_SCL",
|
||||
"AP_TS_I2C_SDA",
|
||||
"AP_TS_I2C_SCL",
|
||||
"RCAM_RST_L",
|
||||
"",
|
||||
"AP_EDP_BKLTEN",
|
||||
"AP_BRD_ID1",
|
||||
"BOOT_CONFIG_4",
|
||||
"AMP_IRQ_L",
|
||||
"EDP_BRIJ_I2C_SDA",
|
||||
"EDP_BRIJ_I2C_SCL",
|
||||
"EN_PP3300_DX_EDP",
|
||||
"SD_CD_ODL",
|
||||
"BT_UART_RTS",
|
||||
"BT_UART_CTS",
|
||||
"BT_UART_RXD",
|
||||
"BT_UART_TXD",
|
||||
"AMP_I2C_SDA",
|
||||
"AMP_I2C_SCL",
|
||||
"AP_BRD_ID3",
|
||||
"",
|
||||
"AP_EC_SPI_CLK",
|
||||
"AP_EC_SPI_CS_L",
|
||||
"AP_EC_SPI_MISO",
|
||||
"AP_EC_SPI_MOSI",
|
||||
"FORCED_USB_BOOT",
|
||||
"AMP_BCLK",
|
||||
"AMP_LRCLK",
|
||||
"AMP_DOUT",
|
||||
"AMP_DIN",
|
||||
"AP_BRD_ID2",
|
||||
"PEN_PDCT_L",
|
||||
"HP_MCLK",
|
||||
"HP_BCLK",
|
||||
"HP_LRCLK",
|
||||
"HP_DOUT",
|
||||
"HP_DIN",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"BT_SLIMBUS_DATA",
|
||||
"BT_SLIMBUS_CLK",
|
||||
"AMP_RESET_L",
|
||||
"",
|
||||
"FCAM_VSYNC",
|
||||
"",
|
||||
"AP_SKU_ID1",
|
||||
"EC_WOV_BCLK",
|
||||
"EC_WOV_LRCLK",
|
||||
"EC_WOV_DOUT",
|
||||
"",
|
||||
"",
|
||||
"AP_H1_SPI_MISO",
|
||||
"AP_H1_SPI_MOSI",
|
||||
"AP_H1_SPI_CLK",
|
||||
"AP_H1_SPI_CS_L",
|
||||
"",
|
||||
"AP_SPI_CS0_L",
|
||||
"AP_SPI_MOSI",
|
||||
"AP_SPI_MISO",
|
||||
"",
|
||||
"",
|
||||
"AP_SPI_CLK",
|
||||
"",
|
||||
"RFFE6_CLK",
|
||||
"RFFE6_DATA",
|
||||
"BOOT_CONFIG_1",
|
||||
"BOOT_CONFIG_2",
|
||||
"BOOT_CONFIG_0",
|
||||
"EDP_BRIJ_EN",
|
||||
"",
|
||||
"USB_HS_TX_EN",
|
||||
"UIM2_DATA",
|
||||
"UIM2_CLK",
|
||||
"UIM2_RST",
|
||||
"UIM2_PRESENT",
|
||||
"UIM1_DATA",
|
||||
"UIM1_CLK",
|
||||
"UIM1_RST",
|
||||
"",
|
||||
"AP_SKU_ID2",
|
||||
"SDM_GRFC_8",
|
||||
"SDM_GRFC_9",
|
||||
"AP_RST_REQ",
|
||||
"HP_IRQ",
|
||||
"TS_RESET_L",
|
||||
"PEN_EJECT_ODL",
|
||||
"HUB_RST_L",
|
||||
"FP_TO_AP_IRQ",
|
||||
"AP_EC_INT_L",
|
||||
"",
|
||||
"",
|
||||
"TS_INT_L",
|
||||
"AP_SUSPEND_L",
|
||||
"SDM_GRFC_3",
|
||||
"",
|
||||
"H1_AP_INT_ODL",
|
||||
"QLINK_REQ",
|
||||
"QLINK_EN",
|
||||
"SDM_GRFC_2",
|
||||
"BOOT_CONFIG_3",
|
||||
"WMSS_RESET_L",
|
||||
"SDM_GRFC_0",
|
||||
"SDM_GRFC_1",
|
||||
"RFFE3_DATA",
|
||||
"RFFE3_CLK",
|
||||
"RFFE4_DATA",
|
||||
"RFFE4_CLK",
|
||||
"RFFE5_DATA",
|
||||
"RFFE5_CLK",
|
||||
"GNSS_EN",
|
||||
"WCI2_LTE_COEX_RXD",
|
||||
"WCI2_LTE_COEX_TXD",
|
||||
"AP_RAM_ID1",
|
||||
"AP_RAM_ID2",
|
||||
"RFFE1_DATA",
|
||||
"RFFE1_CLK";
|
||||
};
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Cheza board device tree source
|
||||
*
|
||||
* Copyright 2018 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-cheza.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Cheza (rev2)";
|
||||
compatible = "google,cheza-rev2", "qcom,sdm845";
|
||||
|
||||
/*
|
||||
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: Technically pp3500_a is not the exact same signal as
|
||||
* pp3500_a_vbob (there's a load switch between them and the EC can
|
||||
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
|
||||
* view they are the same.
|
||||
*/
|
||||
pp3500_a:
|
||||
pp3500_a_vbob: pp3500-a-vbob-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_bob";
|
||||
|
||||
/*
|
||||
* Comes on automatically when pp5000_ldo comes on, which
|
||||
* comes on automatically when ppvar_sys comes on
|
||||
*/
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3500000>;
|
||||
regulator-max-microvolt = <3500000>;
|
||||
|
||||
vin-supply = <&ppvar_sys>;
|
||||
};
|
||||
|
||||
pp3300_dx_edp: pp3300-dx-edp-regulator {
|
||||
/* Yes, it's really 3.5 despite the name of the signal */
|
||||
regulator-min-microvolt = <3500000>;
|
||||
regulator-max-microvolt = <3500000>;
|
||||
|
||||
vin-supply = <&pp3500_a>;
|
||||
};
|
||||
};
|
||||
|
||||
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
|
||||
|
||||
/*
|
||||
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
|
||||
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
|
||||
* prevents the system from booting.
|
||||
*/
|
||||
&src_pp3000_l19a {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
|
||||
&src_pp3300_l22a {
|
||||
/delete-property/regulator-boot-on;
|
||||
/delete-property/regulator-always-on;
|
||||
};
|
||||
|
||||
&src_pp3300_l28a {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
};
|
||||
|
||||
&src_vreg_bob {
|
||||
regulator-min-microvolt = <3500000>;
|
||||
regulator-max-microvolt = <3500000>;
|
||||
vin-supply = <&pp3500_a_vbob>;
|
||||
};
|
||||
|
||||
/*
|
||||
* NON-REGULATOR OVERRIDES
|
||||
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
|
||||
*/
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
|
||||
&tlmm {
|
||||
gpio-line-names = "AP_SPI_FP_MISO",
|
||||
"AP_SPI_FP_MOSI",
|
||||
"AP_SPI_FP_CLK",
|
||||
"AP_SPI_FP_CS_L",
|
||||
"UART_AP_TX_DBG_RX",
|
||||
"UART_DBG_TX_AP_RX",
|
||||
"BRIJ_SUSPEND",
|
||||
"FP_RST_L",
|
||||
"FCAM_EN",
|
||||
"",
|
||||
"EDP_BRIJ_IRQ",
|
||||
"EC_IN_RW_ODL",
|
||||
"",
|
||||
"RCAM_MCLK",
|
||||
"FCAM_MCLK",
|
||||
"",
|
||||
"RCAM_EN",
|
||||
"CCI0_SDA",
|
||||
"CCI0_SCL",
|
||||
"CCI1_SDA",
|
||||
"CCI1_SCL",
|
||||
"FCAM_RST_L",
|
||||
"FPMCU_BOOT0",
|
||||
"PEN_RST_L",
|
||||
"PEN_IRQ_L",
|
||||
"FPMCU_SEL_OD",
|
||||
"RCAM_VSYNC",
|
||||
"ESIM_MISO",
|
||||
"ESIM_MOSI",
|
||||
"ESIM_CLK",
|
||||
"ESIM_CS_L",
|
||||
"AP_PEN_1V8_SDA",
|
||||
"AP_PEN_1V8_SCL",
|
||||
"AP_TS_I2C_SDA",
|
||||
"AP_TS_I2C_SCL",
|
||||
"RCAM_RST_L",
|
||||
"",
|
||||
"AP_EDP_BKLTEN",
|
||||
"AP_BRD_ID1",
|
||||
"BOOT_CONFIG_4",
|
||||
"AMP_IRQ_L",
|
||||
"EDP_BRIJ_I2C_SDA",
|
||||
"EDP_BRIJ_I2C_SCL",
|
||||
"EN_PP3300_DX_EDP",
|
||||
"SD_CD_ODL",
|
||||
"BT_UART_RTS",
|
||||
"BT_UART_CTS",
|
||||
"BT_UART_RXD",
|
||||
"BT_UART_TXD",
|
||||
"AMP_I2C_SDA",
|
||||
"AMP_I2C_SCL",
|
||||
"AP_BRD_ID3",
|
||||
"",
|
||||
"AP_EC_SPI_CLK",
|
||||
"AP_EC_SPI_CS_L",
|
||||
"AP_EC_SPI_MISO",
|
||||
"AP_EC_SPI_MOSI",
|
||||
"FORCED_USB_BOOT",
|
||||
"AMP_BCLK",
|
||||
"AMP_LRCLK",
|
||||
"AMP_DOUT",
|
||||
"AMP_DIN",
|
||||
"AP_BRD_ID2",
|
||||
"PEN_PDCT_L",
|
||||
"HP_MCLK",
|
||||
"HP_BCLK",
|
||||
"HP_LRCLK",
|
||||
"HP_DOUT",
|
||||
"HP_DIN",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"BT_SLIMBUS_DATA",
|
||||
"BT_SLIMBUS_CLK",
|
||||
"AMP_RESET_L",
|
||||
"",
|
||||
"FCAM_VSYNC",
|
||||
"",
|
||||
"AP_SKU_ID1",
|
||||
"EC_WOV_BCLK",
|
||||
"EC_WOV_LRCLK",
|
||||
"EC_WOV_DOUT",
|
||||
"",
|
||||
"",
|
||||
"AP_H1_SPI_MISO",
|
||||
"AP_H1_SPI_MOSI",
|
||||
"AP_H1_SPI_CLK",
|
||||
"AP_H1_SPI_CS_L",
|
||||
"",
|
||||
"AP_SPI_CS0_L",
|
||||
"AP_SPI_MOSI",
|
||||
"AP_SPI_MISO",
|
||||
"",
|
||||
"",
|
||||
"AP_SPI_CLK",
|
||||
"",
|
||||
"RFFE6_CLK",
|
||||
"RFFE6_DATA",
|
||||
"BOOT_CONFIG_1",
|
||||
"BOOT_CONFIG_2",
|
||||
"BOOT_CONFIG_0",
|
||||
"EDP_BRIJ_EN",
|
||||
"",
|
||||
"USB_HS_TX_EN",
|
||||
"UIM2_DATA",
|
||||
"UIM2_CLK",
|
||||
"UIM2_RST",
|
||||
"UIM2_PRESENT",
|
||||
"UIM1_DATA",
|
||||
"UIM1_CLK",
|
||||
"UIM1_RST",
|
||||
"",
|
||||
"AP_SKU_ID2",
|
||||
"SDM_GRFC_8",
|
||||
"SDM_GRFC_9",
|
||||
"AP_RST_REQ",
|
||||
"HP_IRQ",
|
||||
"TS_RESET_L",
|
||||
"PEN_EJECT_ODL",
|
||||
"HUB_RST_L",
|
||||
"FP_TO_AP_IRQ",
|
||||
"AP_EC_INT_L",
|
||||
"",
|
||||
"",
|
||||
"TS_INT_L",
|
||||
"AP_SUSPEND_L",
|
||||
"SDM_GRFC_3",
|
||||
"",
|
||||
"H1_AP_INT_ODL",
|
||||
"QLINK_REQ",
|
||||
"QLINK_EN",
|
||||
"SDM_GRFC_2",
|
||||
"BOOT_CONFIG_3",
|
||||
"WMSS_RESET_L",
|
||||
"SDM_GRFC_0",
|
||||
"SDM_GRFC_1",
|
||||
"RFFE3_DATA",
|
||||
"RFFE3_CLK",
|
||||
"RFFE4_DATA",
|
||||
"RFFE4_CLK",
|
||||
"RFFE5_DATA",
|
||||
"RFFE5_CLK",
|
||||
"GNSS_EN",
|
||||
"WCI2_LTE_COEX_RXD",
|
||||
"WCI2_LTE_COEX_TXD",
|
||||
"AP_RAM_ID1",
|
||||
"AP_RAM_ID2",
|
||||
"RFFE1_DATA",
|
||||
"RFFE1_CLK";
|
||||
};
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Cheza board device tree source
|
||||
*
|
||||
* Copyright 2018 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-cheza.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Cheza (rev3+)";
|
||||
compatible = "google,cheza", "qcom,sdm845";
|
||||
};
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
|
||||
&tlmm {
|
||||
gpio-line-names = "AP_SPI_FP_MISO",
|
||||
"AP_SPI_FP_MOSI",
|
||||
"AP_SPI_FP_CLK",
|
||||
"AP_SPI_FP_CS_L",
|
||||
"UART_AP_TX_DBG_RX",
|
||||
"UART_DBG_TX_AP_RX",
|
||||
"BRIJ_SUSPEND",
|
||||
"FP_RST_L",
|
||||
"FCAM_EN",
|
||||
"",
|
||||
"EDP_BRIJ_IRQ",
|
||||
"EC_IN_RW_ODL",
|
||||
"",
|
||||
"RCAM_MCLK",
|
||||
"FCAM_MCLK",
|
||||
"",
|
||||
"RCAM_EN",
|
||||
"CCI0_SDA",
|
||||
"CCI0_SCL",
|
||||
"CCI1_SDA",
|
||||
"CCI1_SCL",
|
||||
"FCAM_RST_L",
|
||||
"FPMCU_BOOT0",
|
||||
"PEN_RST_L",
|
||||
"PEN_IRQ_L",
|
||||
"FPMCU_SEL_OD",
|
||||
"RCAM_VSYNC",
|
||||
"ESIM_MISO",
|
||||
"ESIM_MOSI",
|
||||
"ESIM_CLK",
|
||||
"ESIM_CS_L",
|
||||
"AP_PEN_1V8_SDA",
|
||||
"AP_PEN_1V8_SCL",
|
||||
"AP_TS_I2C_SDA",
|
||||
"AP_TS_I2C_SCL",
|
||||
"RCAM_RST_L",
|
||||
"",
|
||||
"AP_EDP_BKLTEN",
|
||||
"AP_BRD_ID0",
|
||||
"BOOT_CONFIG_4",
|
||||
"AMP_IRQ_L",
|
||||
"EDP_BRIJ_I2C_SDA",
|
||||
"EDP_BRIJ_I2C_SCL",
|
||||
"EN_PP3300_DX_EDP",
|
||||
"SD_CD_ODL",
|
||||
"BT_UART_RTS",
|
||||
"BT_UART_CTS",
|
||||
"BT_UART_RXD",
|
||||
"BT_UART_TXD",
|
||||
"AMP_I2C_SDA",
|
||||
"AMP_I2C_SCL",
|
||||
"AP_BRD_ID2",
|
||||
"",
|
||||
"AP_EC_SPI_CLK",
|
||||
"AP_EC_SPI_CS_L",
|
||||
"AP_EC_SPI_MISO",
|
||||
"AP_EC_SPI_MOSI",
|
||||
"FORCED_USB_BOOT",
|
||||
"AMP_BCLK",
|
||||
"AMP_LRCLK",
|
||||
"AMP_DOUT",
|
||||
"AMP_DIN",
|
||||
"AP_BRD_ID1",
|
||||
"PEN_PDCT_L",
|
||||
"HP_MCLK",
|
||||
"HP_BCLK",
|
||||
"HP_LRCLK",
|
||||
"HP_DOUT",
|
||||
"HP_DIN",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"BT_SLIMBUS_DATA",
|
||||
"BT_SLIMBUS_CLK",
|
||||
"AMP_RESET_L",
|
||||
"",
|
||||
"FCAM_VSYNC",
|
||||
"",
|
||||
"AP_SKU_ID0",
|
||||
"EC_WOV_BCLK",
|
||||
"EC_WOV_LRCLK",
|
||||
"EC_WOV_DOUT",
|
||||
"",
|
||||
"",
|
||||
"AP_H1_SPI_MISO",
|
||||
"AP_H1_SPI_MOSI",
|
||||
"AP_H1_SPI_CLK",
|
||||
"AP_H1_SPI_CS_L",
|
||||
"",
|
||||
"AP_SPI_CS0_L",
|
||||
"AP_SPI_MOSI",
|
||||
"AP_SPI_MISO",
|
||||
"",
|
||||
"",
|
||||
"AP_SPI_CLK",
|
||||
"",
|
||||
"RFFE6_CLK",
|
||||
"RFFE6_DATA",
|
||||
"BOOT_CONFIG_1",
|
||||
"BOOT_CONFIG_2",
|
||||
"BOOT_CONFIG_0",
|
||||
"EDP_BRIJ_EN",
|
||||
"",
|
||||
"USB_HS_TX_EN",
|
||||
"UIM2_DATA",
|
||||
"UIM2_CLK",
|
||||
"UIM2_RST",
|
||||
"UIM2_PRESENT",
|
||||
"UIM1_DATA",
|
||||
"UIM1_CLK",
|
||||
"UIM1_RST",
|
||||
"",
|
||||
"AP_SKU_ID1",
|
||||
"SDM_GRFC_8",
|
||||
"SDM_GRFC_9",
|
||||
"AP_RST_REQ",
|
||||
"HP_IRQ",
|
||||
"TS_RESET_L",
|
||||
"PEN_EJECT_ODL",
|
||||
"HUB_RST_L",
|
||||
"FP_TO_AP_IRQ",
|
||||
"AP_EC_INT_L",
|
||||
"",
|
||||
"",
|
||||
"TS_INT_L",
|
||||
"AP_SUSPEND_L",
|
||||
"SDM_GRFC_3",
|
||||
/*
|
||||
* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
|
||||
* call it BIOS_FLASH_WP_R_L.
|
||||
*/
|
||||
"AP_FLASH_WP_L",
|
||||
"H1_AP_INT_ODL",
|
||||
"QLINK_REQ",
|
||||
"QLINK_EN",
|
||||
"SDM_GRFC_2",
|
||||
"BOOT_CONFIG_3",
|
||||
"WMSS_RESET_L",
|
||||
"SDM_GRFC_0",
|
||||
"SDM_GRFC_1",
|
||||
"RFFE3_DATA",
|
||||
"RFFE3_CLK",
|
||||
"RFFE4_DATA",
|
||||
"RFFE4_CLK",
|
||||
"RFFE5_DATA",
|
||||
"RFFE5_CLK",
|
||||
"GNSS_EN",
|
||||
"WCI2_LTE_COEX_RXD",
|
||||
"WCI2_LTE_COEX_TXD",
|
||||
"AP_RAM_ID0",
|
||||
"AP_RAM_ID1",
|
||||
"RFFE1_DATA",
|
||||
"RFFE1_CLK";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue