drm/amd/display: Combine dce80 and dce100 i2c hw functions
[Why] There are two versions of the hw function pointers: one for dce80 and one for all other versions. These paired functions are nearly identical. dce80 and dce100 should not require different i2c access functions. [How] Combine each pair of functions into a single function. Mostly the new functions are based on the dce100 versions as those versions are newer, support more features, and were more maintained. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David Francis
Alex Deucher
parent
d75de8ac94
commit
728098352e
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@ -58,18 +58,7 @@ static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
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return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
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}
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static void set_speed_hw_dce80(
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struct dce_i2c_hw *dce_i2c_hw,
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uint32_t speed)
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{
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if (speed) {
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REG_UPDATE_N(SPEED, 2,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), dce_i2c_hw->reference_frequency / speed,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
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}
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}
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static void set_speed_hw_dce100(
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static void set_speed(
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struct dce_i2c_hw *dce_i2c_hw,
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uint32_t speed)
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{
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@ -86,6 +75,7 @@ static void set_speed_hw_dce100(
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
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}
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}
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bool dce_i2c_hw_engine_acquire_engine(
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struct dce_i2c_hw *dce_i2c_hw,
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struct ddc *ddc)
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@ -172,7 +162,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
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return NULL;
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}
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static bool setup_engine_hw_dce100(
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static bool setup_engine(
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struct dce_i2c_hw *dce_i2c_hw)
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{
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uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
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@ -206,72 +196,11 @@ static bool setup_engine_hw_dce100(
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return true;
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}
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static bool setup_engine_hw_dce80(
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struct dce_i2c_hw *dce_i2c_hw)
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{
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/* Program pin select */
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{
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REG_UPDATE_6(DC_I2C_CONTROL,
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DC_I2C_GO, 0,
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DC_I2C_SOFT_RESET, 0,
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DC_I2C_SEND_RESET, 0,
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DC_I2C_SW_STATUS_RESET, 1,
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DC_I2C_TRANSACTION_COUNT, 0,
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DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
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}
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/* Program time limit */
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{
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REG_UPDATE_2(SETUP,
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DC_I2C_DDC1_TIME_LIMIT, I2C_SETUP_TIME_LIMIT_DCE,
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DC_I2C_DDC1_ENABLE, 1);
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}
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/* Program HW priority
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* set to High - interrupt software I2C at any time
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* Enable restart of SW I2C that was interrupted by HW
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* disable queuing of software while I2C is in use by HW
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*/
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{
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REG_UPDATE_2(DC_I2C_ARBITRATION,
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DC_I2C_NO_QUEUED_SW_GO, 0,
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DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL);
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}
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return true;
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}
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static void process_channel_reply_hw_dce80(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_reply_transaction_data *reply)
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{
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uint32_t length = reply->length;
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uint8_t *buffer = reply->data;
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REG_SET_3(DC_I2C_DATA, 0,
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DC_I2C_INDEX, length - 1,
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DC_I2C_DATA_RW, 1,
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DC_I2C_INDEX_WRITE, 1);
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while (length) {
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/* after reading the status,
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* if the I2C operation executed successfully
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* (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
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* should read data bytes from I2C circular data buffer
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*/
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uint32_t i2c_data;
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REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
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*buffer++ = i2c_data;
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--length;
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}
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}
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static void process_channel_reply_hw_dce100(
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static void process_channel_reply(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_reply_transaction_data *reply)
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{
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@ -404,7 +333,7 @@ static void execute_transaction_hw(
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dce_i2c_hw->transaction_count = 0;
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dce_i2c_hw->buffer_used_bytes = 0;
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}
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static bool process_transaction_hw_dce80(
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static bool process_transaction(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_request_transaction_data *request)
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{
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@ -414,135 +343,49 @@ static bool process_transaction_hw_dce80(
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bool last_transaction = false;
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uint32_t value = 0;
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{
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last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
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(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
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last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
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(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
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switch (dce_i2c_hw->transaction_count) {
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case 0:
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REG_UPDATE_5(DC_I2C_TRANSACTION0,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 1:
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REG_UPDATE_5(DC_I2C_TRANSACTION1,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 2:
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REG_UPDATE_5(DC_I2C_TRANSACTION2,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 3:
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REG_UPDATE_5(DC_I2C_TRANSACTION3,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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default:
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/* TODO Warning ? */
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break;
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}
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}
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/* Write the I2C address and I2C data
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* into the hardware circular buffer, one byte per entry.
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* As an example, the 7-bit I2C slave address for CRT monitor
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* for reading DDC/EDID information is 0b1010001.
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* For an I2C send operation, the LSB must be programmed to 0;
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* for I2C receive operation, the LSB must be programmed to 1.
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*/
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{
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if (dce_i2c_hw->transaction_count == 0) {
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value = REG_SET_4(DC_I2C_DATA, 0,
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DC_I2C_DATA_RW, false,
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DC_I2C_DATA, request->address,
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DC_I2C_INDEX, 0,
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DC_I2C_INDEX_WRITE, 1);
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} else
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value = REG_SET_2(DC_I2C_DATA, 0,
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DC_I2C_DATA_RW, false,
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DC_I2C_DATA, request->address);
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if (!(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)) {
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while (length) {
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REG_SET_2(DC_I2C_DATA, value,
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DC_I2C_INDEX_WRITE, 0,
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DC_I2C_DATA, *buffer++);
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--length;
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}
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}
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}
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++dce_i2c_hw->transaction_count;
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dce_i2c_hw->buffer_used_bytes += length + 1;
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return last_transaction;
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}
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#define STOP_TRANS_PREDICAT \
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((dce_i2c_hw->transaction_count == 3) || \
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(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) || \
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(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ))
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#define SET_I2C_TRANSACTION(id) \
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do { \
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REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5, \
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FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1, \
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FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1, \
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FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0, \
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FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)), \
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FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length); \
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if (STOP_TRANS_PREDICAT) \
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last_transaction = true; \
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} while (false)
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static bool process_transaction_hw_dce100(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_request_transaction_data *request)
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{
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uint32_t length = request->length;
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uint8_t *buffer = request->data;
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uint32_t value = 0;
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bool last_transaction = false;
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switch (dce_i2c_hw->transaction_count) {
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case 0:
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SET_I2C_TRANSACTION(0);
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REG_UPDATE_5(DC_I2C_TRANSACTION0,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 1:
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SET_I2C_TRANSACTION(1);
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REG_UPDATE_5(DC_I2C_TRANSACTION1,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 2:
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SET_I2C_TRANSACTION(2);
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REG_UPDATE_5(DC_I2C_TRANSACTION2,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 3:
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SET_I2C_TRANSACTION(3);
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REG_UPDATE_5(DC_I2C_TRANSACTION3,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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default:
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/* TODO Warning ? */
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break;
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}
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/* Write the I2C address and I2C data
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* into the hardware circular buffer, one byte per entry.
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* As an example, the 7-bit I2C slave address for CRT monitor
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@ -828,24 +671,24 @@ bool dce_i2c_submit_command_hw(
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return result;
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}
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static const struct dce_i2c_hw_funcs dce100_i2c_hw_funcs = {
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.setup_engine = setup_engine_hw_dce100,
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.set_speed = set_speed_hw_dce100,
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.setup_engine = setup_engine,
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.set_speed = set_speed,
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.get_speed = get_speed_hw,
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.release_engine = release_engine_hw,
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.process_transaction = process_transaction_hw_dce100,
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.process_channel_reply = process_channel_reply_hw_dce100,
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.process_transaction = process_transaction,
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.process_channel_reply = process_channel_reply,
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.is_hw_busy = is_hw_busy,
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.get_channel_status = get_channel_status_hw,
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.execute_transaction = execute_transaction_hw,
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.disable_i2c_hw_engine = disable_i2c_hw_engine
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};
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static const struct dce_i2c_hw_funcs dce80_i2c_hw_funcs = {
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.setup_engine = setup_engine_hw_dce80,
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.set_speed = set_speed_hw_dce80,
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.setup_engine = setup_engine,
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.set_speed = set_speed,
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.get_speed = get_speed_hw,
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.release_engine = release_engine_hw,
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.process_transaction = process_transaction_hw_dce80,
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.process_channel_reply = process_channel_reply_hw_dce80,
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.process_transaction = process_transaction,
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.process_channel_reply = process_channel_reply,
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.is_hw_busy = is_hw_busy,
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.get_channel_status = get_channel_status_hw,
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.execute_transaction = execute_transaction_hw,
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