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MIPS: Fix typo when reporting cache and ftlb errors for ImgTec cores 

Introduced by the following two commits:
75b5b5e0a2
"MIPS: Add support for FTLBs"
6de2045185
"MIPS: Add printing of ES bit for Imgtec cores when cache error occurs"

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reported-by: Matheus Almeida <Matheus.Almeida@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: stable@vger.kernel.org # v3.14+
Patchwork: https://patchwork.linux-mips.org/patch/6980/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras 2014-05-21 12:35:00 +01:00 committed by Ralf Baechle
parent defb79f086
commit 721a920539
1 changed files with 2 additions and 2 deletions
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4
arch/mips/kernel/traps.c
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@ -1545,7 +1545,7 @@ asmlinkage void cache_parity_error(void)
reg_val & (1<<30) ? "secondary" : "primary", reg_val & (1<<30) ? "secondary" : "primary",
reg_val & (1<<31) ? "data" : "insn"); reg_val & (1<<31) ? "data" : "insn");
if (cpu_has_mips_r2 && if (cpu_has_mips_r2 &&
((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
pr_err("Error bits: %s%s%s%s%s%s%s%s\n", pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
reg_val & (1<<29) ? "ED " : "", reg_val & (1<<29) ? "ED " : "",
reg_val & (1<<28) ? "ET " : "", reg_val & (1<<28) ? "ET " : "",
@ -1585,7 +1585,7 @@ asmlinkage void do_ftlb(void)
/* For the moment, report the problem and hang. */ /* For the moment, report the problem and hang. */
if (cpu_has_mips_r2 && if (cpu_has_mips_r2 &&
((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
read_c0_ecc()); read_c0_ecc());
pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());