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i2c: qup: Correct duty cycle for FM and FM+ 

The I2C spec UM10204 Rev. 6 specifies the following timings.

           Standard      Fast Mode     Fast Mode Plus
SCL low    4.7us         1.3us         0.5us
SCL high   4.0us         0.6us         0.26us

This results in a 33%/66% duty cycle as opposed to the 50%/50% duty cycle
used for Standard-mode.

Add High Time Divider settings to correct duty cycle for FM(400kHz) and
FM+(1MHz).

Signed-off-by: Austin Christ <austinwc@codeaurora.org>
Reviewed-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Austin Christ 2018-05-10 10:13:56 -06:00 committed by Wolfram Sang
parent 109b8c42b7
commit 71fbafcc45
1 changed files with 8 additions and 2 deletions
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10
drivers/i2c/busses/i2c-qup.c
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@ -1855,9 +1855,15 @@ nodma:
size = QUP_INPUT_FIFO_SIZE(io_mode);
qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
hs_div = 3;
qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
if (clk_freq <= I2C_STANDARD_FREQ) {
fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
} else {
/* 33%/66% duty cycle */
fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
}
/*
* Time it takes for a byte to be clocked out on the bus.