arm64: Add Juno board device tree.
This adds support for ARM's Juno development board (rev 0). It enables most of the board peripherals: UART, I2C, USB, MMC and 100Mb ethernet. There is no support at the moment for clock setting and HDLCD driver which depends on it. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Liviu Dudau
Arnd Bergmann
parent
e9d4ac655b
commit
71f867ec13
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@ -1,4 +1,5 @@
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dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
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always := $(dtb-y)
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@ -0,0 +1,44 @@
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/*
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* ARM Juno Platform clocks
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*
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* Copyright (c) 2013-2014 ARM Ltd
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*
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* This file is licensed under a dual GPLv2 or BSD license.
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*
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*/
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/* SoC fixed clocks */
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soc_uartclk: refclk72738khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <7273800>;
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clock-output-names = "juno:uartclk";
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};
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soc_usb48mhz: clk48mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "clk48mhz";
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};
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soc_smc50mhz: clk50mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "smc_clk";
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_faxiclk: refclk533mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <533000000>;
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clock-output-names = "faxi_clk";
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};
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@ -0,0 +1,129 @@
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/*
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* ARM Juno Platform motherboard peripherals
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*
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* Copyright (c) 2013-2014 ARM Ltd
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*
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* This file is licensed under a dual GPLv2 or BSD license.
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*
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*/
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mb_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "juno_mb:clk24mhz";
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};
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mb_clk25mhz: clk25mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "juno_mb:clk25mhz";
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};
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motherboard {
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compatible = "arm,vexpress,v2p-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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model = "V2M-Juno";
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arm,hbi = <0x252>;
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arm,vexpress,site = <0>;
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arm,v2m-memory-map = "rs1";
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mb_fixed_3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "MCC_SB_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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ethernet@2,00000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <2 0x00000000 0x10000>;
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interrupts = <3>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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clocks = <&mb_clk25mhz>;
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vdd33a-supply = <&mb_fixed_3v3>;
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vddvario-supply = <&mb_fixed_3v3>;
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};
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usb@5,00000000 {
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compatible = "nxp,usb-isp1763";
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reg = <5 0x00000000 0x20000>;
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bus-width = <16>;
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interrupts = <4>;
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};
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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mmci@050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x050000 0x1000>;
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interrupts = <5>;
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/* cd-gpios = <&v2m_mmc_gpios 0 0>;
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wp-gpios = <&v2m_mmc_gpios 1 0>; */
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max-frequency = <12000000>;
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vmmc-supply = <&mb_fixed_3v3>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <8>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <8>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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wdt@0f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x10000>;
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interrupts = <7>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x10000>;
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interrupts = <9>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "timclken1", "apb_pclk";
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x10000>;
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interrupts = <9>;
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clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
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clock-names = "timclken1", "apb_pclk";
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x10000>;
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interrupts = <0>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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};
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};
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};
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@ -0,0 +1,218 @@
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/*
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* ARM Ltd. Juno Platform
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*
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* Copyright (c) 2013-2014 ARM Ltd.
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*
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* This file is licensed under a dual GPLv2 or BSD license.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "ARM Juno development board (r0)";
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compatible = "arm,juno", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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stdout-path = &soc_uart0;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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A57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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};
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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};
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A53_1: cpu@101 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
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};
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A53_2: cpu@102 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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};
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A53_3: cpu@103 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* last 16MB of the first memory area is reserved for secure world use by firmware */
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reg = <0x00000000 0x80000000 0x0 0x7f000000>,
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<0x00000008 0x80000000 0x1 0x80000000>;
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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<0x0 0x2c02f000 0 0x2000>,
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<0x0 0x2c04f000 0 0x2000>,
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<0x0 0x2c06f000 0 0x2000>;
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
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};
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/include/ "juno-clocks.dtsi"
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dma@7ff00000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0x7ff00000 0 0x1000>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_faxiclk>;
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clock-names = "apb_pclk";
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};
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soc_uart0: uart@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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i2c@7ffa0000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x7ffa0000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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i2c-sda-hold-time-ns = <500>;
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clocks = <&soc_smc50mhz>;
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dvi0: dvi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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};
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dvi1: dvi-transmitter@71 {
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compatible = "nxp,tda998x";
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reg = <0x71>;
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};
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};
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ohci@7ffb0000 {
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compatible = "generic-ohci";
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reg = <0x0 0x7ffb0000 0x0 0x10000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_usb48mhz>;
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};
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ehci@7ffc0000 {
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compatible = "generic-ehci";
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reg = <0x0 0x7ffc0000 0x0 0x10000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_usb48mhz>;
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};
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memory-controller@7ffd0000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0 0x7ffd0000 0 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 15>;
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interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>;
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/include/ "juno-motherboard.dtsi"
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};
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};
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