ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) and board specific timing configs. Atmel has two different HW designs for its CPU modules: the first one (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up resistor and PHYAD[1-2] to pull down resistors. As a result, Ronetix design will have its PHY available at address 0x1 and Embest design at 0x7. By defining both phys we're letting the phy core detect the one actually available on the MDIO bus. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -36,6 +36,36 @@
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macb0: ethernet@f0028000 {
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phy-mode = "rgmii";
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <0x1>;
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interrupt-parent = <&pioB>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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txen-skew-ps = <800>;
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txc-skew-ps = <3000>;
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rxdv-skew-ps = <400>;
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rxc-skew-ps = <3000>;
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rxd0-skew-ps = <400>;
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rxd1-skew-ps = <400>;
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rxd2-skew-ps = <400>;
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rxd3-skew-ps = <400>;
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};
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ethernet-phy@7 {
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reg = <0x7>;
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interrupt-parent = <&pioB>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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txen-skew-ps = <800>;
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txc-skew-ps = <3000>;
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rxdv-skew-ps = <400>;
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rxc-skew-ps = <3000>;
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rxd0-skew-ps = <400>;
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rxd1-skew-ps = <400>;
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rxd2-skew-ps = <400>;
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rxd3-skew-ps = <400>;
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};
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};
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pmc: pmc@fffffc00 {
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