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drm/amd/display: Assume active upper layer owns the HW cursor 

[why]
The current logic checks if there's an upper pipe whose viewport
completely covers the current pipe viewport.
This fails in pipe splitting case as you can have layer 1 pipe that
crosses the two layer 0 pipes where it's contained in both, but neither
covers it completely, hence we allow the cursor on both layers.

[How]
Instead of trying to "sum up" rectangles from the higher level pipes
which could leave gaps and would not work generically, we will assume if
there's an upper layer that is active, it will control the HW cursor.

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Krunoslav Kovac 2021-06-22 18:42:28 -04:00 committed by Alex Deucher
parent 1e9653a41a
commit 71e433ee91
1 changed files with 4 additions and 10 deletions
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14
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -3180,24 +3180,18 @@ void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
{ {
struct pipe_ctx *test_pipe; struct pipe_ctx *test_pipe;
const struct rect *r1 = &pipe_ctx->plane_res.scl_data.recout, *r2; int cur_layer = pipe_ctx->plane_state->layer_index;
int r1_r = r1->x + r1->width, r1_b = r1->y + r1->height, r2_r, r2_b;
/** /**
* Disable the cursor if there's another pipe above this with a * Disable the cursor if there's there's an upper layer active,
* plane that contains this pipe's viewport to prevent double cursor * assume it's the one owning the cursor
* and incorrect scaling artifacts.
*/ */
for (test_pipe = pipe_ctx->top_pipe; test_pipe; for (test_pipe = pipe_ctx->top_pipe; test_pipe;
test_pipe = test_pipe->top_pipe) { test_pipe = test_pipe->top_pipe) {
if (!test_pipe->plane_state->visible) if (!test_pipe->plane_state->visible)
continue; continue;
r2 = &test_pipe->plane_res.scl_data.recout; if (test_pipe->plane_state->layer_index < cur_layer)
r2_r = r2->x + r2->width;
r2_b = r2->y + r2->height;
if (r1->x >= r2->x && r1->y >= r2->y && r1_r <= r2_r && r1_b <= r2_b)
return true; return true;
} }