Blackfin arch: make sure we include the fix for SPORT hysteresis when reprogramming clocks
As pointed out by Appalayagari Sreedhar, make sure we include the fix for SPORT hysteresis when reprogramming clocks. Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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@ -78,6 +78,9 @@ ENTRY(_start_dma_code)
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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@ -94,6 +94,9 @@ ENTRY(_start_dma_code)
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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@ -77,6 +77,9 @@ ENTRY(_start_dma_code)
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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