mmc: renesas_sdhi: only check CMD status for HS400 manual correction
R-Car Gen3 cannot use correction error status with HS400. HS200: CMD and DAT signal timing are based on CLK signal. HS400: CMD signal is based on CLK. DAT signal is based on DS signal. In HS400, CMD signal is 200MHz(SDR). DAT signal is 200MHz(DDR). Center position of signal is different between CMD and DAT. TAP position should be adjusted to the center position of CMD signal. DAT sampling timing is adjusted by HS400 calibration circuit regardless of TAP position. Refer to renesas_sdhi_adjust_hs400mode_enable(). However, correction error status contains CMD and DAT status in HS400 (DAT signal is not masked in HS400). Therefore, correction error status cannot use in HS400. It means that auto correction cannot be uses in HS400. Manual correction can change to the correct TAP position by ignoring DAT correction error status and using only CMD correction status. Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com> [wsa: refactored patch from BSP] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217114034.13290-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -250,6 +250,7 @@ static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
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#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
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#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
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#define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
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#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
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/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
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@ -265,6 +266,10 @@ static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
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#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
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#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_SMPCMP register */
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#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
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#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
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#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
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#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
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@ -494,6 +499,7 @@ static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
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static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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unsigned long new_tap = host->tap_set;
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u32 val;
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val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
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@ -503,15 +509,34 @@ static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
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/* Change TAP position according to correction status */
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if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
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return true; /* Need re-tune */
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else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
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host->tap_set = (host->tap_set + 1) % host->tap_num;
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else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
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host->tap_set = (host->tap_set - 1) % host->tap_num;
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else
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return false;
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if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
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host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
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/*
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* With HS400, the DAT signal is based on DS, not CLK.
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* Therefore, use only CMD status.
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*/
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u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
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SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
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if (!smpcmp)
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return false; /* no error in CMD signal */
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else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP)
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new_tap++;
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else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN)
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new_tap--;
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else
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return true; /* need retune */
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} else {
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if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
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return true; /* need retune */
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else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
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new_tap++;
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else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
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new_tap--;
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else
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return false;
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}
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host->tap_set = (new_tap % host->tap_num);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
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host->tap_set / (use_4tap ? 2 : 1));
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