Merge branch 'clk-qcom' into clk-next
* clk-qcom: Revert "clk: qcom: regmap-mux: add pipe clk implementation" Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" clk: qcom: rcg2: Cache CFG register updates for parked RCGs clk: qcom: add sc8280xp GCC driver dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings clk: qcom: gcc-msm8976: Add modem reset dt-bindings: clk: qcom: gcc-msm8976: Add modem reset clk: qcom: gcc-msm8976: Set floor ops for SDCC dt-bindings: clock: qcom,gcc-apq8064: Fix typo in compatible and split apq8084 clk: qcom: smd: Update MSM8976 RPM clocks. clk: qcom: gcc-msm8998: add SSC-related clocks dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks dt-bindings: clock: qcom,rpmcc: add clocks property dt-bindings: clock: qcom,rpmcc: convert to dtschema clk: qcom: lpass: Add support for LPASS clock controller for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: regmap-mux: add pipe clk implementation
This commit is contained in:
Stephen Boyd
commit
71cc785d29
|
|
@ -20,12 +20,10 @@ description: |
|
|||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8084.
|
||||
|
||||
See also::
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-apq8084";
|
||||
reg = <0xfc400000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8280xp.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc8280xp
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO reference clock
|
||||
- description: Sleep clock
|
||||
- description: UFS memory first RX symbol clock
|
||||
- description: UFS memory second RX symbol clock
|
||||
- description: UFS memory first TX symbol clock
|
||||
- description: UFS card first RX symbol clock
|
||||
- description: UFS card second RX symbol clock
|
||||
- description: UFS card first TX symbol clock
|
||||
- description: Primary USB SuperSpeed pipe clock
|
||||
- description: USB4 PHY pipegmux clock source
|
||||
- description: USB4 PHY DP gmux clock source
|
||||
- description: USB4 PHY sys piegmux clock source
|
||||
- description: USB4 PHY PCIe pipe clock
|
||||
- description: USB4 PHY router max pipe clock
|
||||
- description: Primary USB4 RX0 clock
|
||||
- description: Primary USB4 RX1 clock
|
||||
- description: Secondary USB SuperSpeed pipe clock
|
||||
- description: Second USB4 PHY pipegmux clock source
|
||||
- description: Second USB4 PHY DP gmux clock source
|
||||
- description: Second USB4 PHY sys pipegmux clock source
|
||||
- description: Second USB4 PHY PCIe pipe clock
|
||||
- description: Second USB4 PHY router max pipe clock
|
||||
- description: Secondary USB4 RX0 clock
|
||||
- description: Secondary USB4 RX1 clock
|
||||
- description: Multiport USB first SupserSpeed pipe clock
|
||||
- description: Multiport USB second SuperSpeed pipe clock
|
||||
- description: PCIe 2a pipe clock
|
||||
- description: PCIe 2b pipe clock
|
||||
- description: PCIe 3a pipe clock
|
||||
- description: PCIe 3b pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 389
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8280xp";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_1_clk>,
|
||||
<&ufs_card_tx_symbol_0_clk>,
|
||||
<&usb_0_ssphy>,
|
||||
<&gcc_usb4_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx1_clk>,
|
||||
<&usb_1_ssphy>,
|
||||
<&gcc_usb4_1_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx1_clk>,
|
||||
<&usb_2_ssphy>,
|
||||
<&usb_3_ssphy>,
|
||||
<&pcie2a_lane>,
|
||||
<&pcie2b_lane>,
|
||||
<&pcie3a_lane>,
|
||||
<&pcie3b_lane>,
|
||||
<&pcie4_lane>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&rxc1_ref_clk>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
Qualcomm RPM Clock Controller Binding
|
||||
------------------------------------------------
|
||||
The RPM is a dedicated hardware engine for managing the shared
|
||||
SoC resources in order to keep the lowest power profile. It
|
||||
communicates with other hardware subsystems via shared memory
|
||||
and accepts clock requests, aggregates the requests and turns
|
||||
the clocks on/off or scales them on demand.
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following. The generic
|
||||
compatible "qcom,rpmcc" should be also included.
|
||||
|
||||
"qcom,rpmcc-mdm9607", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8226", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8936", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8953", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8976", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8992",·"qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8994",·"qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcm2290", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sdm660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6115", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6125", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
|
||||
and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
|
||||
is an "active" clock, which means that the consumer only care that the
|
||||
clock is available when the apps CPU subsystem is active, i.e. not
|
||||
suspended or in deep idle. If it is important that the clock keeps running
|
||||
during system suspend, you need to specify the non-active clock, the one
|
||||
not containing *_A_* in the enumerator name.
|
||||
|
||||
Example:
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm RPM Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description: |
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
|
||||
come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
|
||||
an "active" clock, which means that the consumer only care that the clock is
|
||||
available when the apps CPU subsystem is active, i.e. not suspended or in
|
||||
deep idle. If it is important that the clock keeps running during system
|
||||
suspend, you need to specify the non-active clock, the one not containing
|
||||
*_A_* in the enumerator name.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,rpmcc-apq8060
|
||||
- qcom,rpmcc-apq8064
|
||||
- qcom,rpmcc-ipq806x
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
- qcom,rpmcc-msm8992
|
||||
- qcom,rpmcc-msm8994
|
||||
- qcom,rpmcc-msm8996
|
||||
- qcom,rpmcc-msm8998
|
||||
- qcom,rpmcc-qcm2290
|
||||
- qcom,rpmcc-qcs404
|
||||
- qcom,rpmcc-sdm660
|
||||
- qcom,rpmcc-sm6115
|
||||
- qcom,rpmcc-sm6125
|
||||
- const: qcom,rpmcc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rpm {
|
||||
rpm-requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock control module which supports the
|
||||
clocks and power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
|
||||
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
|
||||
properties:
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
- qcom,sc7280-lpassaudiocc
|
||||
- qcom,sc7280-lpasscorecc
|
||||
- qcom,sc7280-lpasshm
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc7280-lpassaudiocc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: lpass_aon_cc_main_rcg_clk_src
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO active only source
|
||||
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: iface
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-lpasshm
|
||||
- qcom,sc7280-lpasscorecc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_audiocc: clock-controller@3300000 {
|
||||
compatible = "qcom,sc7280-lpassaudiocc";
|
||||
reg = <0x3300000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
|
||||
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
|
||||
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_hm: clock-controller@3c00000 {
|
||||
compatible = "qcom,sc7280-lpasshm";
|
||||
reg = <0x3c00000 0x28>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpasscore: clock-controller@3900000 {
|
||||
compatible = "qcom,sc7280-lpasscorecc";
|
||||
reg = <0x3900000 0x50000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
lpass_aon: clock-controller@3380000 {
|
||||
compatible = "qcom,sc7280-lpassaoncc";
|
||||
reg = <0x3380000 0x30000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -45,6 +45,10 @@ properties:
|
|||
- qcom,rpm-qcm2290
|
||||
- qcom,rpm-qcs404
|
||||
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/qcom,rpmcc.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
qcom,smd-channels:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: Channel name used for the RPM communication
|
||||
|
|
|
|||
|
|
@ -419,6 +419,15 @@ config SC_GCC_8180X
|
|||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
I2C, USB, UFS, SDCC, etc.
|
||||
|
||||
config SC_GCC_8280XP
|
||||
tristate "SC8280XP Global Clock Controller"
|
||||
select QCOM_GDSC
|
||||
depends on COMMON_CLK_QCOM
|
||||
help
|
||||
Support for the global clock controller on SC8280XP devices.
|
||||
Say Y if you want to use peripheral devices such as UART, SPI,
|
||||
I2C, USB, UFS, SDCC, etc.
|
||||
|
||||
config SC_GPUCC_7180
|
||||
tristate "SC7180 Graphics Clock Controller"
|
||||
select SC_GCC_7180
|
||||
|
|
@ -452,6 +461,16 @@ config SC_LPASS_CORECC_7180
|
|||
Say Y if you want to use LPASS clocks and power domains of the LPASS
|
||||
core clock controller.
|
||||
|
||||
config SC_LPASS_CORECC_7280
|
||||
tristate "SC7280 LPASS Core & Audio Clock Controller"
|
||||
select SC_GCC_7280
|
||||
select QCOM_GDSC
|
||||
help
|
||||
Support for the LPASS(Low Power Audio Subsystem) core and audio clock
|
||||
controller on SC7280 devices.
|
||||
Say Y if you want to use LPASS clocks and power domains of the LPASS
|
||||
core clock controller.
|
||||
|
||||
config SC_MSS_7180
|
||||
tristate "SC7180 Modem Clock Controller"
|
||||
select SC_GCC_7180
|
||||
|
|
|
|||
|
|
@ -67,10 +67,12 @@ obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
|
|||
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
|
||||
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
|
||||
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
|
||||
obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o
|
||||
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
|
||||
obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
|
||||
obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
|
||||
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
|
||||
obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
|
||||
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
|
||||
obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
|
||||
obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
|
|||
* @freq_tbl: frequency table
|
||||
* @clkr: regmap clock handle
|
||||
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
|
||||
* @parked_cfg: cached value of the CFG register for parked RCGs
|
||||
*/
|
||||
struct clk_rcg2 {
|
||||
u32 cmd_rcgr;
|
||||
|
|
@ -150,6 +151,7 @@ struct clk_rcg2 {
|
|||
const struct freq_tbl *freq_tbl;
|
||||
struct clk_regmap clkr;
|
||||
u8 cfg_off;
|
||||
u32 parked_cfg;
|
||||
};
|
||||
|
||||
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
|
||||
|
|
|
|||
|
|
@ -73,16 +73,11 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw)
|
|||
return (cmd & CMD_ROOT_OFF) == 0;
|
||||
}
|
||||
|
||||
static u8 clk_rcg2_get_parent(struct clk_hw *hw)
|
||||
static u8 __clk_rcg2_get_parent(struct clk_hw *hw, u32 cfg)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
u32 cfg;
|
||||
int i, ret;
|
||||
|
||||
ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
if (ret)
|
||||
goto err;
|
||||
int i;
|
||||
|
||||
cfg &= CFG_SRC_SEL_MASK;
|
||||
cfg >>= CFG_SRC_SEL_SHIFT;
|
||||
|
|
@ -91,12 +86,27 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
|
|||
if (cfg == rcg->parent_map[i].cfg)
|
||||
return i;
|
||||
|
||||
err:
|
||||
pr_debug("%s: Clock %s has invalid parent, using default.\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 clk_rcg2_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 cfg;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
if (ret) {
|
||||
pr_debug("%s: Unable to read CFG register for %s\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return 0;
|
||||
}
|
||||
|
||||
return __clk_rcg2_get_parent(hw, cfg);
|
||||
}
|
||||
|
||||
static int update_config(struct clk_rcg2 *rcg)
|
||||
{
|
||||
int count, ret;
|
||||
|
|
@ -163,12 +173,10 @@ calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
|
|||
}
|
||||
|
||||
static unsigned long
|
||||
clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
__clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
u32 hid_div, m = 0, n = 0, mode = 0, mask;
|
||||
|
||||
if (rcg->mnd_width) {
|
||||
mask = BIT(rcg->mnd_width) - 1;
|
||||
|
|
@ -189,6 +197,17 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
return calc_rate(parent_rate, m, n, mode, hid_div);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 cfg;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
|
||||
return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
|
||||
}
|
||||
|
||||
static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
|
||||
struct clk_rate_request *req,
|
||||
enum freq_policy policy)
|
||||
|
|
@ -262,7 +281,8 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
|
|||
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
|
||||
}
|
||||
|
||||
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
|
||||
u32 *_cfg)
|
||||
{
|
||||
u32 cfg, mask, d_val, not2d_val, n_minus_m;
|
||||
struct clk_hw *hw = &rcg->clkr.hw;
|
||||
|
|
@ -304,15 +324,27 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
|||
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
||||
if (rcg->mnd_width && f->n && (f->m != f->n))
|
||||
cfg |= CFG_MODE_DUAL_EDGE;
|
||||
return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
|
||||
mask, cfg);
|
||||
|
||||
*_cfg &= ~mask;
|
||||
*_cfg |= cfg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
|
||||
{
|
||||
u32 cfg;
|
||||
int ret;
|
||||
|
||||
ret = __clk_rcg2_configure(rcg, f);
|
||||
ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __clk_rcg2_configure(rcg, f, &cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -979,11 +1011,12 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* In case clock is disabled, update the CFG, M, N and D registers
|
||||
* and don't hit the update bit of CMD register.
|
||||
* In case clock is disabled, update the M, N and D registers, cache
|
||||
* the CFG value in parked_cfg and don't hit the update bit of CMD
|
||||
* register.
|
||||
*/
|
||||
if (!__clk_is_enabled(hw->clk))
|
||||
return __clk_rcg2_configure(rcg, f);
|
||||
if (!clk_hw_is_enabled(hw))
|
||||
return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg);
|
||||
|
||||
return clk_rcg2_shared_force_enable_clear(hw, f);
|
||||
}
|
||||
|
|
@ -1007,6 +1040,11 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Write back the stored configuration corresponding to current rate */
|
||||
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = update_config(rcg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1017,13 +1055,12 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw)
|
|||
static void clk_rcg2_shared_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
u32 cfg;
|
||||
|
||||
/*
|
||||
* Store current configuration as switching to safe source would clear
|
||||
* the SRC and DIV of CFG register
|
||||
*/
|
||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
|
||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
|
||||
|
||||
/*
|
||||
* Park the RCG at a safe configuration - sourced off of safe source.
|
||||
|
|
@ -1041,17 +1078,52 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw)
|
|||
update_config(rcg);
|
||||
|
||||
clk_rcg2_clear_force_enable(hw);
|
||||
}
|
||||
|
||||
/* Write back the stored configuration corresponding to current rate */
|
||||
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
|
||||
static u8 clk_rcg2_shared_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
|
||||
/* If the shared rcg is parked use the cached cfg instead */
|
||||
if (!clk_hw_is_enabled(hw))
|
||||
return __clk_rcg2_get_parent(hw, rcg->parked_cfg);
|
||||
|
||||
return clk_rcg2_get_parent(hw);
|
||||
}
|
||||
|
||||
static int clk_rcg2_shared_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
|
||||
/* If the shared rcg is parked only update the cached cfg */
|
||||
if (!clk_hw_is_enabled(hw)) {
|
||||
rcg->parked_cfg &= ~CFG_SRC_SEL_MASK;
|
||||
rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return clk_rcg2_set_parent(hw, index);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
|
||||
/* If the shared rcg is parked use the cached cfg instead */
|
||||
if (!clk_hw_is_enabled(hw))
|
||||
return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg);
|
||||
|
||||
return clk_rcg2_recalc_rate(hw, parent_rate);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_rcg2_shared_ops = {
|
||||
.enable = clk_rcg2_shared_enable,
|
||||
.disable = clk_rcg2_shared_disable,
|
||||
.get_parent = clk_rcg2_get_parent,
|
||||
.set_parent = clk_rcg2_set_parent,
|
||||
.recalc_rate = clk_rcg2_recalc_rate,
|
||||
.get_parent = clk_rcg2_shared_get_parent,
|
||||
.set_parent = clk_rcg2_shared_set_parent,
|
||||
.recalc_rate = clk_rcg2_shared_recalc_rate,
|
||||
.determine_rate = clk_rcg2_determine_rate,
|
||||
.set_rate = clk_rcg2_shared_set_rate,
|
||||
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
|
||||
|
|
|
|||
|
|
@ -563,17 +563,19 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
|
|||
.num_clks = ARRAY_SIZE(msm8974_clks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
|
||||
QCOM_SMD_RPM_BUS_CLK, 2);
|
||||
DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
|
||||
|
||||
static struct clk_smd_rpm *msm8976_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
|
||||
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
||||
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
|
||||
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
|
||||
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
|
||||
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
|
||||
[RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk,
|
||||
[RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
||||
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
|
||||
|
|
@ -586,8 +588,6 @@ static struct clk_smd_rpm *msm8976_clks[] = {
|
|||
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
|
||||
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
|
||||
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
|
||||
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
|
||||
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
|
||||
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
|
||||
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
|
||||
|
|
|
|||
|
|
@ -1486,7 +1486,7 @@ static const struct clk_init_data sdcc1_apps_clk_src_8976v1_1_init = {
|
|||
.name = "sdcc1_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_v1_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_v1_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 sdcc1_apps_clk_src = {
|
||||
|
|
@ -1499,7 +1499,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
|
|||
.name = "sdcc1_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1547,7 +1547,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
|
|||
.name = "sdcc2_apps_clk_src",
|
||||
.parent_data = gcc_parent_data_4_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
|
||||
.ops = &clk_rcg2_ops,
|
||||
.ops = &clk_rcg2_floor_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -4056,6 +4056,7 @@ static const struct qcom_reset_map gcc_msm8976_resets[] = {
|
|||
[RST_CAMSS_CSI_VFE1_BCR] = { 0x58070 },
|
||||
[RST_CAMSS_VFE1_BCR] = { 0x5807c },
|
||||
[RST_CAMSS_CPP_BCR] = { 0x58080 },
|
||||
[RST_MSS_BCR] = { 0x71000 },
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_msm8976_gdscs[] = {
|
||||
|
|
|
|||
|
|
@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_im_sleep_clk = {
|
||||
.halt_reg = 0x4300c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x4300c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "gcc_im_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch aggre2_snoc_north_axi_clk = {
|
||||
.halt_reg = 0x83010,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x83010,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "aggre2_snoc_north_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch ssc_xo_clk = {
|
||||
.halt_reg = 0x63018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x63018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "ssc_xo_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch ssc_cnoc_ahbs_clk = {
|
||||
.halt_reg = 0x6300c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x6300c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "ssc_cnoc_ahbs_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc pcie_0_gdsc = {
|
||||
.gdscr = 0x6b004,
|
||||
.gds_hw_ctrl = 0x0,
|
||||
|
|
@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
|
|||
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
|
||||
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
|
||||
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
|
||||
[GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
|
||||
[AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
|
||||
[SSC_XO] = &ssc_xo_clk.clkr,
|
||||
[SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_msm8998_gdscs[] = {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,838 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_LPASS_AON_CC_PLL_OUT_EVEN,
|
||||
P_LPASS_AON_CC_PLL_OUT_MAIN,
|
||||
P_LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC,
|
||||
P_LPASS_AON_CC_PLL_OUT_ODD,
|
||||
P_LPASS_AUDIO_CC_PLL_OUT_AUX,
|
||||
P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC,
|
||||
P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK,
|
||||
};
|
||||
|
||||
static const struct pll_vco zonda_vco[] = {
|
||||
{ 595200000UL, 3600000000UL, 0 },
|
||||
};
|
||||
|
||||
/* 1128.96MHz configuration */
|
||||
static const struct alpha_pll_config lpass_audio_cc_pll_config = {
|
||||
.l = 0x3a,
|
||||
.alpha = 0xcccc,
|
||||
.config_ctl_val = 0x08200920,
|
||||
.config_ctl_hi_val = 0x05002001,
|
||||
.config_ctl_hi1_val = 0x00000000,
|
||||
.user_ctl_val = 0x03000101,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll lpass_audio_cc_pll = {
|
||||
.offset = 0x0,
|
||||
.vco_table = zonda_vco,
|
||||
.num_vco = ARRAY_SIZE(zonda_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_pll",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = 0,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_zonda_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_div_table post_div_table_lpass_audio_cc_pll_out_aux2[] = {
|
||||
{ 0x1, 2 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll_postdiv lpass_audio_cc_pll_out_aux2 = {
|
||||
.offset = 0x0,
|
||||
.post_div_shift = 8,
|
||||
.post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
|
||||
.num_post_div = ARRAY_SIZE(post_div_table_lpass_audio_cc_pll_out_aux2),
|
||||
.width = 2,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_pll_out_aux2",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_zonda_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
/* 614.4 MHz configuration */
|
||||
static const struct alpha_pll_config lpass_aon_cc_pll_config = {
|
||||
.l = 0x20,
|
||||
.alpha = 0x0,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0x329A299C,
|
||||
.user_ctl_val = 0x00005100,
|
||||
.user_ctl_hi_val = 0x00000805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll lpass_aon_cc_pll = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_pll",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = 0,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_even[] = {
|
||||
{ 0x1, 2 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_even = {
|
||||
.offset = 0x0,
|
||||
.post_div_shift = 8,
|
||||
.post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
|
||||
.num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_even),
|
||||
.width = 4,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_pll_out_even",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_lucid_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_odd[] = {
|
||||
{ 0x5, 5 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_odd = {
|
||||
.offset = 0x0,
|
||||
.post_div_shift = 12,
|
||||
.post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
|
||||
.num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_odd),
|
||||
.width = 4,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_pll_out_odd",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_postdiv_lucid_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map lpass_audio_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_LPASS_AUDIO_CC_PLL_OUT_AUX, 3 },
|
||||
{ P_LPASS_AON_CC_PLL_OUT_ODD, 5 },
|
||||
{ P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 6 },
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src;
|
||||
static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src;
|
||||
|
||||
static const struct clk_parent_data lpass_audio_cc_parent_data_0[] = {
|
||||
{ .index = 0 },
|
||||
{ .hw = &lpass_audio_cc_pll.clkr.hw },
|
||||
{ .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
|
||||
{ .hw = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map lpass_aon_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_LPASS_AON_CC_PLL_OUT_EVEN, 4 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data lpass_aon_cc_parent_data_0[] = {
|
||||
{ .index = 0 },
|
||||
{ .hw = &lpass_aon_cc_pll_out_even.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map lpass_aon_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_LPASS_AON_CC_PLL_OUT_ODD, 1 },
|
||||
{ P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data lpass_aon_cc_parent_data_1[] = {
|
||||
{ .index = 0 },
|
||||
{ .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
|
||||
{ .hw = &lpass_audio_cc_pll_out_main_div_clk_src.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_lpass_aon_cc_main_rcg_clk_src[] = {
|
||||
F(38400000, P_LPASS_AON_CC_PLL_OUT_EVEN, 8, 0, 0),
|
||||
F(76800000, P_LPASS_AON_CC_PLL_OUT_EVEN, 4, 0, 0),
|
||||
F(153600000, P_LPASS_AON_CC_PLL_OUT_EVEN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
|
||||
.cmd_rcgr = 0x1000,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_aon_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_aon_cc_main_rcg_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_main_rcg_clk_src",
|
||||
.parent_data = lpass_aon_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
|
||||
.flags = CLK_OPS_PARENT_ENABLE,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_aon_cc_tx_mclk_rcg_clk_src = {
|
||||
.cmd_rcgr = 0x13004,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_aon_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_tx_mclk_rcg_clk_src",
|
||||
.parent_data = lpass_aon_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_1),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src = {
|
||||
.reg = 0x48,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "lpass_audio_cc_pll_out_aux2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_pll_out_aux2.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src = {
|
||||
.reg = 0x3c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "lpass_audio_cc_pll_out_main_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_aon_cc_cdiv_tx_mclk_div_clk_src = {
|
||||
.reg = 0x13010,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "lpass_aon_cc_cdiv_tx_mclk_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_aon_cc_pll_out_main_cdiv_div_clk_src = {
|
||||
.reg = 0x80,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "lpass_aon_cc_pll_out_main_cdiv_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_lpass_audio_cc_ext_mclk0_clk_src[] = {
|
||||
F(256000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 32),
|
||||
F(352800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 32),
|
||||
F(512000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 16),
|
||||
F(705600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 16),
|
||||
F(768000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 16),
|
||||
F(1024000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 8),
|
||||
F(1411200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 8),
|
||||
F(1536000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 8),
|
||||
F(2048000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 4),
|
||||
F(2822400, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 4),
|
||||
F(3072000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 4),
|
||||
F(4096000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 2),
|
||||
F(5644800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 2),
|
||||
F(6144000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 2),
|
||||
F(8192000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 0, 0),
|
||||
F(9600000, P_BI_TCXO, 2, 0, 0),
|
||||
F(11289600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 0, 0),
|
||||
F(12288000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 0, 0),
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(22579200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 5, 0, 0),
|
||||
F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_audio_cc_ext_mclk0_clk_src = {
|
||||
.cmd_rcgr = 0x20004,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_audio_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_ext_mclk0_clk_src",
|
||||
.parent_data = lpass_audio_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_audio_cc_ext_mclk1_clk_src = {
|
||||
.cmd_rcgr = 0x21004,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_audio_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_ext_mclk1_clk_src",
|
||||
.parent_data = lpass_audio_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_audio_cc_rx_mclk_clk_src = {
|
||||
.cmd_rcgr = 0x24004,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_audio_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_rx_mclk_clk_src",
|
||||
.parent_data = lpass_audio_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_audio_cc_cdiv_rx_mclk_div_clk_src = {
|
||||
.reg = 0x240d0,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "lpass_audio_cc_cdiv_rx_mclk_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_aon_cc_audio_hm_h_clk;
|
||||
|
||||
static struct clk_branch lpass_audio_cc_codec_mem0_clk = {
|
||||
.halt_reg = 0x1e004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_codec_mem0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_codec_mem1_clk = {
|
||||
.halt_reg = 0x1e008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_codec_mem1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_codec_mem2_clk = {
|
||||
.halt_reg = 0x1e00c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e00c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_codec_mem2_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_codec_mem_clk = {
|
||||
.halt_reg = 0x1e000,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_codec_mem_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_ext_mclk0_clk = {
|
||||
.halt_reg = 0x20018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x20018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_ext_mclk0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_ext_mclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_ext_mclk1_clk = {
|
||||
.halt_reg = 0x21018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x21018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_ext_mclk1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_ext_mclk1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_rx_mclk_2x_clk = {
|
||||
.halt_reg = 0x240cc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x240cc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_rx_mclk_2x_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_audio_cc_rx_mclk_clk = {
|
||||
.halt_reg = 0x240d4,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x240d4,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_audio_cc_rx_mclk_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_aon_cc_audio_hm_h_clk = {
|
||||
.halt_reg = 0x9014,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9014,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_audio_hm_h_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_main_rcg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_aon_cc_va_mem0_clk = {
|
||||
.halt_reg = 0x9028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9028,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_va_mem0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_main_rcg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_aon_cc_tx_mclk_2x_clk = {
|
||||
.halt_reg = 0x1300c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1300c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_tx_mclk_2x_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_aon_cc_tx_mclk_clk = {
|
||||
.halt_reg = 0x13014,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x13014,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_aon_cc_tx_mclk_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = {
|
||||
.gdscr = 0x9090,
|
||||
.pd = {
|
||||
.name = "lpass_aon_cc_lpass_audio_hm_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
|
||||
[LPASS_AON_CC_AUDIO_HM_H_CLK] = &lpass_aon_cc_audio_hm_h_clk.clkr,
|
||||
[LPASS_AON_CC_VA_MEM0_CLK] = &lpass_aon_cc_va_mem0_clk.clkr,
|
||||
[LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr,
|
||||
[LPASS_AON_CC_MAIN_RCG_CLK_SRC] = &lpass_aon_cc_main_rcg_clk_src.clkr,
|
||||
[LPASS_AON_CC_PLL] = &lpass_aon_cc_pll.clkr,
|
||||
[LPASS_AON_CC_PLL_OUT_EVEN] = &lpass_aon_cc_pll_out_even.clkr,
|
||||
[LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC] =
|
||||
&lpass_aon_cc_pll_out_main_cdiv_div_clk_src.clkr,
|
||||
[LPASS_AON_CC_PLL_OUT_ODD] = &lpass_aon_cc_pll_out_odd.clkr,
|
||||
[LPASS_AON_CC_TX_MCLK_2X_CLK] = &lpass_aon_cc_tx_mclk_2x_clk.clkr,
|
||||
[LPASS_AON_CC_TX_MCLK_CLK] = &lpass_aon_cc_tx_mclk_clk.clkr,
|
||||
[LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC] = &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *lpass_aon_cc_sc7280_gdscs[] = {
|
||||
[LPASS_AON_CC_LPASS_AUDIO_HM_GDSC] = &lpass_aon_cc_lpass_audio_hm_gdsc,
|
||||
};
|
||||
|
||||
static struct clk_regmap *lpass_audio_cc_sc7280_clocks[] = {
|
||||
[LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC] = &lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr,
|
||||
[LPASS_AUDIO_CC_CODEC_MEM0_CLK] = &lpass_audio_cc_codec_mem0_clk.clkr,
|
||||
[LPASS_AUDIO_CC_CODEC_MEM1_CLK] = &lpass_audio_cc_codec_mem1_clk.clkr,
|
||||
[LPASS_AUDIO_CC_CODEC_MEM2_CLK] = &lpass_audio_cc_codec_mem2_clk.clkr,
|
||||
[LPASS_AUDIO_CC_CODEC_MEM_CLK] = &lpass_audio_cc_codec_mem_clk.clkr,
|
||||
[LPASS_AUDIO_CC_EXT_MCLK0_CLK] = &lpass_audio_cc_ext_mclk0_clk.clkr,
|
||||
[LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC] = &lpass_audio_cc_ext_mclk0_clk_src.clkr,
|
||||
[LPASS_AUDIO_CC_EXT_MCLK1_CLK] = &lpass_audio_cc_ext_mclk1_clk.clkr,
|
||||
[LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC] = &lpass_audio_cc_ext_mclk1_clk_src.clkr,
|
||||
[LPASS_AUDIO_CC_PLL] = &lpass_audio_cc_pll.clkr,
|
||||
[LPASS_AUDIO_CC_PLL_OUT_AUX2] = &lpass_audio_cc_pll_out_aux2.clkr,
|
||||
[LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr,
|
||||
[LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_main_div_clk_src.clkr,
|
||||
[LPASS_AUDIO_CC_RX_MCLK_2X_CLK] = &lpass_audio_cc_rx_mclk_2x_clk.clkr,
|
||||
[LPASS_AUDIO_CC_RX_MCLK_CLK] = &lpass_audio_cc_rx_mclk_clk.clkr,
|
||||
[LPASS_AUDIO_CC_RX_MCLK_CLK_SRC] = &lpass_audio_cc_rx_mclk_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct regmap_config lpass_audio_cc_sc7280_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
|
||||
.config = &lpass_audio_cc_sc7280_regmap_config,
|
||||
.clks = lpass_audio_cc_sc7280_clocks,
|
||||
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
|
||||
};
|
||||
|
||||
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
|
||||
{ .compatible = "qcom,sc7280-lpassaudiocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
|
||||
|
||||
static void lpassaudio_pm_runtime_disable(void *data)
|
||||
{
|
||||
pm_runtime_disable(data);
|
||||
}
|
||||
|
||||
static void lpassaudio_pm_clk_destroy(void *data)
|
||||
{
|
||||
pm_clk_destroy(data);
|
||||
}
|
||||
|
||||
static int lpassaudio_create_pm_clks(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_add_action_or_reset(&pdev->dev, lpassaudio_pm_runtime_disable, &pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_clk_create(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_add_action_or_reset(&pdev->dev, lpassaudio_pm_clk_destroy, &pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_clk_add(&pdev->dev, "iface");
|
||||
if (ret < 0)
|
||||
dev_err(&pdev->dev, "failed to acquire iface clock\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_cc_desc *desc;
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = lpassaudio_create_pm_clks(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc";
|
||||
lpass_audio_cc_sc7280_regmap_config.max_register = 0x2f000;
|
||||
desc = &lpass_audio_cc_sc7280_desc;
|
||||
|
||||
regmap = qcom_cc_map(pdev, desc);
|
||||
if (IS_ERR(regmap)) {
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
clk_zonda_pll_configure(&lpass_audio_cc_pll, regmap, &lpass_audio_cc_pll_config);
|
||||
|
||||
/* PLL settings */
|
||||
regmap_write(regmap, 0x4, 0x3b);
|
||||
regmap_write(regmap, 0x8, 0xff05);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_mark_last_busy(&pdev->dev);
|
||||
pm_runtime_put_autosuspend(&pdev->dev);
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops lpass_audio_cc_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver lpass_audio_cc_sc7280_driver = {
|
||||
.probe = lpass_audio_cc_sc7280_probe,
|
||||
.driver = {
|
||||
.name = "lpass_audio_cc-sc7280",
|
||||
.of_match_table = lpass_audio_cc_sc7280_match_table,
|
||||
.pm = &lpass_audio_cc_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpass_aon_cc_sc7280_desc = {
|
||||
.config = &lpass_audio_cc_sc7280_regmap_config,
|
||||
.clks = lpass_aon_cc_sc7280_clocks,
|
||||
.num_clks = ARRAY_SIZE(lpass_aon_cc_sc7280_clocks),
|
||||
.gdscs = lpass_aon_cc_sc7280_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id lpass_aon_cc_sc7280_match_table[] = {
|
||||
{ .compatible = "qcom,sc7280-lpassaoncc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpass_aon_cc_sc7280_match_table);
|
||||
|
||||
static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_cc_desc *desc;
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
ret = lpassaudio_create_pm_clks(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
|
||||
lpass_audio_cc_sc7280_regmap_config.max_register = 0xa0008;
|
||||
desc = &lpass_aon_cc_sc7280_desc;
|
||||
|
||||
regmap = qcom_cc_map(pdev, desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
|
||||
|
||||
pm_runtime_mark_last_busy(&pdev->dev);
|
||||
pm_runtime_put_autosuspend(&pdev->dev);
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver lpass_aon_cc_sc7280_driver = {
|
||||
.probe = lpass_aon_cc_sc7280_probe,
|
||||
.driver = {
|
||||
.name = "lpass_aon_cc-sc7280",
|
||||
.of_match_table = lpass_aon_cc_sc7280_match_table,
|
||||
.pm = &lpass_audio_cc_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lpass_audio_cc_sc7280_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&lpass_aon_cc_sc7280_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return platform_driver_register(&lpass_audio_cc_sc7280_driver);
|
||||
}
|
||||
subsys_initcall(lpass_audio_cc_sc7280_init);
|
||||
|
||||
static void __exit lpass_audio_cc_sc7280_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lpass_audio_cc_sc7280_driver);
|
||||
platform_driver_unregister(&lpass_aon_cc_sc7280_driver);
|
||||
}
|
||||
module_exit(lpass_audio_cc_sc7280_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI LPASS_AUDIO_CC SC7280 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,431 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "common.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN,
|
||||
P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC,
|
||||
P_LPASS_CORE_CC_DIG_PLL_OUT_ODD,
|
||||
};
|
||||
|
||||
static const struct pll_vco lucid_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
/* 614.4MHz configuration */
|
||||
static const struct alpha_pll_config lpass_core_cc_dig_pll_config = {
|
||||
.l = 0x20,
|
||||
.alpha = 0x0,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00002261,
|
||||
.config_ctl_hi1_val = 0xB2923BBC,
|
||||
.user_ctl_val = 0x00005100,
|
||||
.user_ctl_hi_val = 0x00050805,
|
||||
.user_ctl_hi1_val = 0x00000000,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll lpass_core_cc_dig_pll = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "lpass_core_cc_dig_pll",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.index = 0,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct clk_div_table post_div_table_lpass_core_cc_dig_pll_out_odd[] = {
|
||||
{ 0x5, 5 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll_postdiv lpass_core_cc_dig_pll_out_odd = {
|
||||
.offset = 0x1000,
|
||||
.post_div_shift = 12,
|
||||
.post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
|
||||
.num_post_div = ARRAY_SIZE(post_div_table_lpass_core_cc_dig_pll_out_odd),
|
||||
.width = 4,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "lpass_core_cc_dig_pll_out_odd",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_dig_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_alpha_pll_postdiv_lucid_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div lpass_core_cc_dig_pll_out_main_div_clk_src = {
|
||||
.reg = 0x1054,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "lpass_core_cc_dig_pll_out_main_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_dig_pll.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static const struct parent_map lpass_core_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
|
||||
{ .index = 0 },
|
||||
{ .hw = &lpass_core_cc_dig_pll_out_odd.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map lpass_core_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 1 },
|
||||
{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 2 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data lpass_core_cc_parent_data_ao_2[] = {
|
||||
{ .index = 1 },
|
||||
{ .hw = &lpass_core_cc_dig_pll.clkr.hw },
|
||||
{ .hw = &lpass_core_cc_dig_pll_out_main_div_clk_src.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_lpass_core_cc_core_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(51200000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 6, 0, 0),
|
||||
F(102400000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 3, 0, 0),
|
||||
F(204800000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_core_cc_core_clk_src = {
|
||||
.cmd_rcgr = 0x1d000,
|
||||
.mnd_width = 8,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_core_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_lpass_core_cc_core_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_core_clk_src",
|
||||
.parent_data = lpass_core_cc_parent_data_ao_2,
|
||||
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_ao_2),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_lpass_core_cc_ext_if0_clk_src[] = {
|
||||
F(256000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 32),
|
||||
F(512000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 16),
|
||||
F(768000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 16),
|
||||
F(1024000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 8),
|
||||
F(1536000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 8),
|
||||
F(2048000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 4),
|
||||
F(3072000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 4),
|
||||
F(4096000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 2),
|
||||
F(6144000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 2),
|
||||
F(8192000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 0, 0),
|
||||
F(9600000, P_BI_TCXO, 2, 0, 0),
|
||||
F(12288000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 0, 0),
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(24576000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_core_cc_ext_if0_clk_src = {
|
||||
.cmd_rcgr = 0x10000,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_core_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_ext_if0_clk_src",
|
||||
.parent_data = lpass_core_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
|
||||
.cmd_rcgr = 0x11000,
|
||||
.mnd_width = 16,
|
||||
.hid_width = 5,
|
||||
.parent_map = lpass_core_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
|
||||
.clkr.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_ext_if1_clk_src",
|
||||
.parent_data = lpass_core_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static struct clk_branch lpass_core_cc_core_clk = {
|
||||
.halt_reg = 0x1f000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0x1f000,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1f000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_core_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_core_cc_ext_if0_ibit_clk = {
|
||||
.halt_reg = 0x10018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_ext_if0_ibit_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_ext_if0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_core_cc_ext_if1_ibit_clk = {
|
||||
.halt_reg = 0x11018,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x11018,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_ext_if1_ibit_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_ext_if1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_core_cc_lpm_core_clk = {
|
||||
.halt_reg = 0x1e000,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_lpm_core_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
|
||||
.halt_reg = 0x1e004,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x1e004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_lpm_mem0_core_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
|
||||
.halt_reg = 0x23000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0x23000,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x23000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data){
|
||||
.name = "lpass_core_cc_sysnoc_mport_core_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&lpass_core_cc_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc lpass_core_cc_lpass_core_hm_gdsc = {
|
||||
.gdscr = 0x0,
|
||||
.pd = {
|
||||
.name = "lpass_core_cc_lpass_core_hm_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
|
||||
[LPASS_CORE_CC_CORE_CLK] = &lpass_core_cc_core_clk.clkr,
|
||||
[LPASS_CORE_CC_CORE_CLK_SRC] = &lpass_core_cc_core_clk_src.clkr,
|
||||
[LPASS_CORE_CC_DIG_PLL] = &lpass_core_cc_dig_pll.clkr,
|
||||
[LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC] =
|
||||
&lpass_core_cc_dig_pll_out_main_div_clk_src.clkr,
|
||||
[LPASS_CORE_CC_DIG_PLL_OUT_ODD] = &lpass_core_cc_dig_pll_out_odd.clkr,
|
||||
[LPASS_CORE_CC_EXT_IF0_CLK_SRC] = &lpass_core_cc_ext_if0_clk_src.clkr,
|
||||
[LPASS_CORE_CC_EXT_IF0_IBIT_CLK] = &lpass_core_cc_ext_if0_ibit_clk.clkr,
|
||||
[LPASS_CORE_CC_EXT_IF1_CLK_SRC] = &lpass_core_cc_ext_if1_clk_src.clkr,
|
||||
[LPASS_CORE_CC_EXT_IF1_IBIT_CLK] = &lpass_core_cc_ext_if1_ibit_clk.clkr,
|
||||
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
|
||||
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
|
||||
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
|
||||
};
|
||||
|
||||
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpass_core_cc_sc7280_desc = {
|
||||
.config = &lpass_core_cc_sc7280_regmap_config,
|
||||
.clks = lpass_core_cc_sc7280_clocks,
|
||||
.num_clks = ARRAY_SIZE(lpass_core_cc_sc7280_clocks),
|
||||
};
|
||||
|
||||
static const struct of_device_id lpass_core_cc_sc7280_match_table[] = {
|
||||
{ .compatible = "qcom,sc7280-lpasscorecc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7280_match_table);
|
||||
|
||||
static struct gdsc *lpass_core_hm_sc7280_gdscs[] = {
|
||||
[LPASS_CORE_CC_LPASS_CORE_HM_GDSC] = &lpass_core_cc_lpass_core_hm_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lpass_core_hm_sc7280_desc = {
|
||||
.config = &lpass_core_cc_sc7280_regmap_config,
|
||||
.gdscs = lpass_core_hm_sc7280_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7280_gdscs),
|
||||
};
|
||||
|
||||
static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_cc_desc *desc;
|
||||
struct regmap *regmap;
|
||||
|
||||
lpass_core_cc_sc7280_regmap_config.name = "lpass_core_cc";
|
||||
lpass_core_cc_sc7280_regmap_config.max_register = 0x4f004;
|
||||
desc = &lpass_core_cc_sc7280_desc;
|
||||
|
||||
regmap = qcom_cc_map(pdev, desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
|
||||
}
|
||||
|
||||
static struct platform_driver lpass_core_cc_sc7280_driver = {
|
||||
.probe = lpass_core_cc_sc7280_probe,
|
||||
.driver = {
|
||||
.name = "lpass_core_cc-sc7280",
|
||||
.of_match_table = lpass_core_cc_sc7280_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int lpass_hm_core_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_cc_desc *desc;
|
||||
|
||||
lpass_core_cc_sc7280_regmap_config.name = "lpass_hm_core";
|
||||
lpass_core_cc_sc7280_regmap_config.max_register = 0x24;
|
||||
desc = &lpass_core_hm_sc7280_desc;
|
||||
|
||||
return qcom_cc_probe_by_index(pdev, 0, desc);
|
||||
}
|
||||
|
||||
static const struct of_device_id lpass_hm_sc7280_match_table[] = {
|
||||
{ .compatible = "qcom,sc7280-lpasshm" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpass_hm_sc7280_match_table);
|
||||
|
||||
static struct platform_driver lpass_hm_sc7280_driver = {
|
||||
.probe = lpass_hm_core_probe,
|
||||
.driver = {
|
||||
.name = "lpass_hm-sc7280",
|
||||
.of_match_table = lpass_hm_sc7280_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lpass_core_cc_sc7280_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&lpass_hm_sc7280_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return platform_driver_register(&lpass_core_cc_sc7280_driver);
|
||||
}
|
||||
subsys_initcall(lpass_core_cc_sc7280_init);
|
||||
|
||||
static void __exit lpass_core_cc_sc7280_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lpass_core_cc_sc7280_driver);
|
||||
platform_driver_unregister(&lpass_hm_sc7280_driver);
|
||||
}
|
||||
module_exit(lpass_core_cc_sc7280_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7280 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -224,6 +224,7 @@
|
|||
#define RST_CAMSS_CSI_VFE1_BCR 7
|
||||
#define RST_CAMSS_VFE1_BCR 8
|
||||
#define RST_CAMSS_CPP_BCR 9
|
||||
#define RST_MSS_BCR 10
|
||||
|
||||
/* GDSCs */
|
||||
#define VENUS_GDSC 0
|
||||
|
|
|
|||
|
|
@ -186,6 +186,10 @@
|
|||
#define UFS_UNIPRO_CORE_CLK_SRC 177
|
||||
#define GCC_MMSS_GPLL0_CLK 178
|
||||
#define HMSS_GPLL0_CLK_SRC 179
|
||||
#define GCC_IM_SLEEP 180
|
||||
#define AGGRE2_SNOC_NORTH_AXI 181
|
||||
#define SSC_XO 182
|
||||
#define SSC_CNOC_AHBS_CLK 183
|
||||
|
||||
#define PCIE_0_GDSC 0
|
||||
#define UFS_GDSC 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,496 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_GPLL0 0
|
||||
#define GCC_GPLL0_OUT_EVEN 1
|
||||
#define GCC_GPLL2 2
|
||||
#define GCC_GPLL4 3
|
||||
#define GCC_GPLL7 4
|
||||
#define GCC_GPLL8 5
|
||||
#define GCC_GPLL9 6
|
||||
#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7
|
||||
#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8
|
||||
#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9
|
||||
#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10
|
||||
#define GCC_AGGRE_UFS_CARD_AXI_CLK 11
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 12
|
||||
#define GCC_AGGRE_USB3_MP_AXI_CLK 13
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14
|
||||
#define GCC_AGGRE_USB3_SEC_AXI_CLK 15
|
||||
#define GCC_AGGRE_USB4_1_AXI_CLK 16
|
||||
#define GCC_AGGRE_USB4_AXI_CLK 17
|
||||
#define GCC_AGGRE_USB_NOC_AXI_CLK 18
|
||||
#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19
|
||||
#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20
|
||||
#define GCC_AHB2PHY0_CLK 21
|
||||
#define GCC_AHB2PHY2_CLK 22
|
||||
#define GCC_BOOT_ROM_AHB_CLK 23
|
||||
#define GCC_CAMERA_AHB_CLK 24
|
||||
#define GCC_CAMERA_HF_AXI_CLK 25
|
||||
#define GCC_CAMERA_SF_AXI_CLK 26
|
||||
#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27
|
||||
#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28
|
||||
#define GCC_CAMERA_THROTTLE_XO_CLK 29
|
||||
#define GCC_CAMERA_XO_CLK 30
|
||||
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32
|
||||
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33
|
||||
#define GCC_CNOC_PCIE0_TUNNEL_CLK 34
|
||||
#define GCC_CNOC_PCIE1_TUNNEL_CLK 35
|
||||
#define GCC_CNOC_PCIE4_QX_CLK 36
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 37
|
||||
#define GCC_DDRSS_PCIE_SF_TBU_CLK 38
|
||||
#define GCC_DISP1_AHB_CLK 39
|
||||
#define GCC_DISP1_HF_AXI_CLK 40
|
||||
#define GCC_DISP1_SF_AXI_CLK 41
|
||||
#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42
|
||||
#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43
|
||||
#define GCC_DISP1_XO_CLK 44
|
||||
#define GCC_DISP_AHB_CLK 45
|
||||
#define GCC_DISP_HF_AXI_CLK 46
|
||||
#define GCC_DISP_SF_AXI_CLK 47
|
||||
#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48
|
||||
#define GCC_DISP_THROTTLE_RT_AXI_CLK 49
|
||||
#define GCC_DISP_XO_CLK 50
|
||||
#define GCC_EMAC0_AXI_CLK 51
|
||||
#define GCC_EMAC0_PTP_CLK 52
|
||||
#define GCC_EMAC0_PTP_CLK_SRC 53
|
||||
#define GCC_EMAC0_RGMII_CLK 54
|
||||
#define GCC_EMAC0_RGMII_CLK_SRC 55
|
||||
#define GCC_EMAC0_SLV_AHB_CLK 56
|
||||
#define GCC_EMAC1_AXI_CLK 57
|
||||
#define GCC_EMAC1_PTP_CLK 58
|
||||
#define GCC_EMAC1_PTP_CLK_SRC 59
|
||||
#define GCC_EMAC1_RGMII_CLK 60
|
||||
#define GCC_EMAC1_RGMII_CLK_SRC 61
|
||||
#define GCC_EMAC1_SLV_AHB_CLK 62
|
||||
#define GCC_GP1_CLK 63
|
||||
#define GCC_GP1_CLK_SRC 64
|
||||
#define GCC_GP2_CLK 65
|
||||
#define GCC_GP2_CLK_SRC 66
|
||||
#define GCC_GP3_CLK 67
|
||||
#define GCC_GP3_CLK_SRC 68
|
||||
#define GCC_GP4_CLK 69
|
||||
#define GCC_GP4_CLK_SRC 70
|
||||
#define GCC_GP5_CLK 71
|
||||
#define GCC_GP5_CLK_SRC 72
|
||||
#define GCC_GPU_CFG_AHB_CLK 73
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 74
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 75
|
||||
#define GCC_GPU_IREF_EN 76
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 77
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 78
|
||||
#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79
|
||||
#define GCC_GPU_TCU_THROTTLE_CLK 80
|
||||
#define GCC_PCIE0_PHY_RCHNG_CLK 81
|
||||
#define GCC_PCIE1_PHY_RCHNG_CLK 82
|
||||
#define GCC_PCIE2A_PHY_RCHNG_CLK 83
|
||||
#define GCC_PCIE2B_PHY_RCHNG_CLK 84
|
||||
#define GCC_PCIE3A_PHY_RCHNG_CLK 85
|
||||
#define GCC_PCIE3B_PHY_RCHNG_CLK 86
|
||||
#define GCC_PCIE4_PHY_RCHNG_CLK 87
|
||||
#define GCC_PCIE_0_AUX_CLK 88
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 89
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 90
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 91
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92
|
||||
#define GCC_PCIE_0_PIPE_CLK 93
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 94
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95
|
||||
#define GCC_PCIE_1_AUX_CLK 96
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 97
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 98
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 99
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100
|
||||
#define GCC_PCIE_1_PIPE_CLK 101
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 102
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103
|
||||
#define GCC_PCIE_2A2B_CLKREF_CLK 104
|
||||
#define GCC_PCIE_2A_AUX_CLK 105
|
||||
#define GCC_PCIE_2A_AUX_CLK_SRC 106
|
||||
#define GCC_PCIE_2A_CFG_AHB_CLK 107
|
||||
#define GCC_PCIE_2A_MSTR_AXI_CLK 108
|
||||
#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109
|
||||
#define GCC_PCIE_2A_PIPE_CLK 110
|
||||
#define GCC_PCIE_2A_PIPE_CLK_SRC 111
|
||||
#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112
|
||||
#define GCC_PCIE_2A_PIPEDIV2_CLK 113
|
||||
#define GCC_PCIE_2A_SLV_AXI_CLK 114
|
||||
#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115
|
||||
#define GCC_PCIE_2B_AUX_CLK 116
|
||||
#define GCC_PCIE_2B_AUX_CLK_SRC 117
|
||||
#define GCC_PCIE_2B_CFG_AHB_CLK 118
|
||||
#define GCC_PCIE_2B_MSTR_AXI_CLK 119
|
||||
#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120
|
||||
#define GCC_PCIE_2B_PIPE_CLK 121
|
||||
#define GCC_PCIE_2B_PIPE_CLK_SRC 122
|
||||
#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123
|
||||
#define GCC_PCIE_2B_PIPEDIV2_CLK 124
|
||||
#define GCC_PCIE_2B_SLV_AXI_CLK 125
|
||||
#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126
|
||||
#define GCC_PCIE_3A3B_CLKREF_CLK 127
|
||||
#define GCC_PCIE_3A_AUX_CLK 128
|
||||
#define GCC_PCIE_3A_AUX_CLK_SRC 129
|
||||
#define GCC_PCIE_3A_CFG_AHB_CLK 130
|
||||
#define GCC_PCIE_3A_MSTR_AXI_CLK 131
|
||||
#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132
|
||||
#define GCC_PCIE_3A_PIPE_CLK 133
|
||||
#define GCC_PCIE_3A_PIPE_CLK_SRC 134
|
||||
#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135
|
||||
#define GCC_PCIE_3A_PIPEDIV2_CLK 136
|
||||
#define GCC_PCIE_3A_SLV_AXI_CLK 137
|
||||
#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138
|
||||
#define GCC_PCIE_3B_AUX_CLK 139
|
||||
#define GCC_PCIE_3B_AUX_CLK_SRC 140
|
||||
#define GCC_PCIE_3B_CFG_AHB_CLK 141
|
||||
#define GCC_PCIE_3B_MSTR_AXI_CLK 142
|
||||
#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143
|
||||
#define GCC_PCIE_3B_PIPE_CLK 144
|
||||
#define GCC_PCIE_3B_PIPE_CLK_SRC 145
|
||||
#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146
|
||||
#define GCC_PCIE_3B_PIPEDIV2_CLK 147
|
||||
#define GCC_PCIE_3B_SLV_AXI_CLK 148
|
||||
#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149
|
||||
#define GCC_PCIE_4_AUX_CLK 150
|
||||
#define GCC_PCIE_4_AUX_CLK_SRC 151
|
||||
#define GCC_PCIE_4_CFG_AHB_CLK 152
|
||||
#define GCC_PCIE_4_CLKREF_CLK 153
|
||||
#define GCC_PCIE_4_MSTR_AXI_CLK 154
|
||||
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155
|
||||
#define GCC_PCIE_4_PIPE_CLK 156
|
||||
#define GCC_PCIE_4_PIPE_CLK_SRC 157
|
||||
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158
|
||||
#define GCC_PCIE_4_PIPEDIV2_CLK 159
|
||||
#define GCC_PCIE_4_SLV_AXI_CLK 160
|
||||
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161
|
||||
#define GCC_PCIE_RSCC_AHB_CLK 162
|
||||
#define GCC_PCIE_RSCC_XO_CLK 163
|
||||
#define GCC_PCIE_RSCC_XO_CLK_SRC 164
|
||||
#define GCC_PCIE_THROTTLE_CFG_CLK 165
|
||||
#define GCC_PDM2_CLK 166
|
||||
#define GCC_PDM2_CLK_SRC 167
|
||||
#define GCC_PDM_AHB_CLK 168
|
||||
#define GCC_PDM_XO4_CLK 169
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 171
|
||||
#define GCC_QMIP_DISP1_AHB_CLK 172
|
||||
#define GCC_QMIP_DISP1_ROT_AHB_CLK 173
|
||||
#define GCC_QMIP_DISP_AHB_CLK 174
|
||||
#define GCC_QMIP_DISP_ROT_AHB_CLK 175
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 179
|
||||
#define GCC_QUPV3_WRAP0_QSPI0_CLK 180
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 181
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 183
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 185
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 187
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 189
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190
|
||||
#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 192
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 194
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 196
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 199
|
||||
#define GCC_QUPV3_WRAP1_QSPI0_CLK 200
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 201
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 203
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 205
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 207
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 209
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210
|
||||
#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 212
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 214
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK 216
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 219
|
||||
#define GCC_QUPV3_WRAP2_QSPI0_CLK 220
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 221
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 223
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 225
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 227
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 229
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230
|
||||
#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 232
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 234
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK 236
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243
|
||||
#define GCC_SDCC2_AHB_CLK 244
|
||||
#define GCC_SDCC2_APPS_CLK 245
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 246
|
||||
#define GCC_SDCC4_AHB_CLK 247
|
||||
#define GCC_SDCC4_APPS_CLK 248
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 249
|
||||
#define GCC_SYS_NOC_USB_AXI_CLK 250
|
||||
#define GCC_UFS_1_CARD_CLKREF_CLK 251
|
||||
#define GCC_UFS_CARD_AHB_CLK 252
|
||||
#define GCC_UFS_CARD_AXI_CLK 253
|
||||
#define GCC_UFS_CARD_AXI_CLK_SRC 254
|
||||
#define GCC_UFS_CARD_CLKREF_CLK 255
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK 256
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK 258
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267
|
||||
#define GCC_UFS_PHY_AHB_CLK 268
|
||||
#define GCC_UFS_PHY_AXI_CLK 269
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 270
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 271
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 273
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282
|
||||
#define GCC_UFS_REF_CLKREF_CLK 283
|
||||
#define GCC_USB2_HS0_CLKREF_CLK 284
|
||||
#define GCC_USB2_HS1_CLKREF_CLK 285
|
||||
#define GCC_USB2_HS2_CLKREF_CLK 286
|
||||
#define GCC_USB2_HS3_CLKREF_CLK 287
|
||||
#define GCC_USB30_MP_MASTER_CLK 288
|
||||
#define GCC_USB30_MP_MASTER_CLK_SRC 289
|
||||
#define GCC_USB30_MP_MOCK_UTMI_CLK 290
|
||||
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291
|
||||
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292
|
||||
#define GCC_USB30_MP_SLEEP_CLK 293
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 294
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 295
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 299
|
||||
#define GCC_USB30_SEC_MASTER_CLK 300
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 301
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 302
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 305
|
||||
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306
|
||||
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307
|
||||
#define GCC_USB3_MP0_CLKREF_CLK 308
|
||||
#define GCC_USB3_MP1_CLKREF_CLK 309
|
||||
#define GCC_USB3_MP_PHY_AUX_CLK 310
|
||||
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311
|
||||
#define GCC_USB3_MP_PHY_COM_AUX_CLK 312
|
||||
#define GCC_USB3_MP_PHY_PIPE_0_CLK 313
|
||||
#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314
|
||||
#define GCC_USB3_MP_PHY_PIPE_1_CLK 315
|
||||
#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 317
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 320
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 322
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 325
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326
|
||||
#define GCC_USB4_1_CFG_AHB_CLK 327
|
||||
#define GCC_USB4_1_DP_CLK 328
|
||||
#define GCC_USB4_1_MASTER_CLK 329
|
||||
#define GCC_USB4_1_MASTER_CLK_SRC 330
|
||||
#define GCC_USB4_1_PHY_DP_CLK_SRC 331
|
||||
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332
|
||||
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336
|
||||
#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337
|
||||
#define GCC_USB4_1_PHY_RX0_CLK 338
|
||||
#define GCC_USB4_1_PHY_RX0_CLK_SRC 339
|
||||
#define GCC_USB4_1_PHY_RX1_CLK 340
|
||||
#define GCC_USB4_1_PHY_RX1_CLK_SRC 341
|
||||
#define GCC_USB4_1_PHY_SYS_CLK_SRC 342
|
||||
#define GCC_USB4_1_PHY_USB_PIPE_CLK 343
|
||||
#define GCC_USB4_1_SB_IF_CLK 344
|
||||
#define GCC_USB4_1_SB_IF_CLK_SRC 345
|
||||
#define GCC_USB4_1_SYS_CLK 346
|
||||
#define GCC_USB4_1_TMU_CLK 347
|
||||
#define GCC_USB4_1_TMU_CLK_SRC 348
|
||||
#define GCC_USB4_CFG_AHB_CLK 349
|
||||
#define GCC_USB4_CLKREF_CLK 350
|
||||
#define GCC_USB4_DP_CLK 351
|
||||
#define GCC_USB4_EUD_CLKREF_CLK 352
|
||||
#define GCC_USB4_MASTER_CLK 353
|
||||
#define GCC_USB4_MASTER_CLK_SRC 354
|
||||
#define GCC_USB4_PHY_DP_CLK_SRC 355
|
||||
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356
|
||||
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357
|
||||
#define GCC_USB4_PHY_PCIE_PIPE_CLK 358
|
||||
#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359
|
||||
#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360
|
||||
#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361
|
||||
#define GCC_USB4_PHY_RX0_CLK 362
|
||||
#define GCC_USB4_PHY_RX0_CLK_SRC 363
|
||||
#define GCC_USB4_PHY_RX1_CLK 364
|
||||
#define GCC_USB4_PHY_RX1_CLK_SRC 365
|
||||
#define GCC_USB4_PHY_SYS_CLK_SRC 366
|
||||
#define GCC_USB4_PHY_USB_PIPE_CLK 367
|
||||
#define GCC_USB4_SB_IF_CLK 368
|
||||
#define GCC_USB4_SB_IF_CLK_SRC 369
|
||||
#define GCC_USB4_SYS_CLK 370
|
||||
#define GCC_USB4_TMU_CLK 371
|
||||
#define GCC_USB4_TMU_CLK_SRC 372
|
||||
#define GCC_VIDEO_AHB_CLK 373
|
||||
#define GCC_VIDEO_AXI0_CLK 374
|
||||
#define GCC_VIDEO_AXI1_CLK 375
|
||||
#define GCC_VIDEO_CVP_THROTTLE_CLK 376
|
||||
#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377
|
||||
#define GCC_VIDEO_XO_CLK 378
|
||||
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380
|
||||
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381
|
||||
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382
|
||||
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_EMAC0_BCR 0
|
||||
#define GCC_EMAC1_BCR 1
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 2
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3
|
||||
#define GCC_PCIE_0_PHY_BCR 4
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5
|
||||
#define GCC_PCIE_0_TUNNEL_BCR 6
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 7
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_1_PHY_BCR 9
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10
|
||||
#define GCC_PCIE_1_TUNNEL_BCR 11
|
||||
#define GCC_PCIE_2A_BCR 12
|
||||
#define GCC_PCIE_2A_LINK_DOWN_BCR 13
|
||||
#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14
|
||||
#define GCC_PCIE_2A_PHY_BCR 15
|
||||
#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16
|
||||
#define GCC_PCIE_2B_BCR 17
|
||||
#define GCC_PCIE_2B_LINK_DOWN_BCR 18
|
||||
#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19
|
||||
#define GCC_PCIE_2B_PHY_BCR 20
|
||||
#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21
|
||||
#define GCC_PCIE_3A_BCR 22
|
||||
#define GCC_PCIE_3A_LINK_DOWN_BCR 23
|
||||
#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24
|
||||
#define GCC_PCIE_3A_PHY_BCR 25
|
||||
#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26
|
||||
#define GCC_PCIE_3B_BCR 27
|
||||
#define GCC_PCIE_3B_LINK_DOWN_BCR 28
|
||||
#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29
|
||||
#define GCC_PCIE_3B_PHY_BCR 30
|
||||
#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31
|
||||
#define GCC_PCIE_4_BCR 32
|
||||
#define GCC_PCIE_4_LINK_DOWN_BCR 33
|
||||
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34
|
||||
#define GCC_PCIE_4_PHY_BCR 35
|
||||
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 37
|
||||
#define GCC_PCIE_PHY_COM_BCR 38
|
||||
#define GCC_PCIE_RSCC_BCR 39
|
||||
#define GCC_QUSB2PHY_HS0_MP_BCR 40
|
||||
#define GCC_QUSB2PHY_HS1_MP_BCR 41
|
||||
#define GCC_QUSB2PHY_HS2_MP_BCR 42
|
||||
#define GCC_QUSB2PHY_HS3_MP_BCR 43
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 44
|
||||
#define GCC_QUSB2PHY_SEC_BCR 45
|
||||
#define GCC_SDCC2_BCR 46
|
||||
#define GCC_SDCC4_BCR 47
|
||||
#define GCC_UFS_CARD_BCR 48
|
||||
#define GCC_UFS_PHY_BCR 49
|
||||
#define GCC_USB2_PHY_PRIM_BCR 50
|
||||
#define GCC_USB2_PHY_SEC_BCR 51
|
||||
#define GCC_USB30_MP_BCR 52
|
||||
#define GCC_USB30_PRIM_BCR 53
|
||||
#define GCC_USB30_SEC_BCR 54
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 55
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 56
|
||||
#define GCC_USB3_PHY_PRIM_BCR 57
|
||||
#define GCC_USB3_PHY_SEC_BCR 58
|
||||
#define GCC_USB3_UNIPHY_MP0_BCR 59
|
||||
#define GCC_USB3_UNIPHY_MP1_BCR 60
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 61
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 62
|
||||
#define GCC_USB3UNIPHY_PHY_MP0_BCR 63
|
||||
#define GCC_USB3UNIPHY_PHY_MP1_BCR 64
|
||||
#define GCC_USB4_1_BCR 65
|
||||
#define GCC_USB4_1_DP_PHY_PRIM_BCR 66
|
||||
#define GCC_USB4_1_DPPHY_AUX_BCR 67
|
||||
#define GCC_USB4_1_PHY_PRIM_BCR 68
|
||||
#define GCC_USB4_BCR 69
|
||||
#define GCC_USB4_DP_PHY_PRIM_BCR 70
|
||||
#define GCC_USB4_DPPHY_AUX_BCR 71
|
||||
#define GCC_USB4_PHY_PRIM_BCR 72
|
||||
#define GCC_USB4PHY_1_PHY_PRIM_BCR 73
|
||||
#define GCC_USB4PHY_PHY_PRIM_BCR 74
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75
|
||||
#define GCC_VIDEO_BCR 76
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 77
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 78
|
||||
|
||||
/* GCC GDSCs */
|
||||
#define PCIE_0_TUNNEL_GDSC 0
|
||||
#define PCIE_1_TUNNEL_GDSC 1
|
||||
#define PCIE_2A_GDSC 2
|
||||
#define PCIE_2B_GDSC 3
|
||||
#define PCIE_3A_GDSC 4
|
||||
#define PCIE_3B_GDSC 5
|
||||
#define PCIE_4_GDSC 6
|
||||
#define UFS_CARD_GDSC 7
|
||||
#define UFS_PHY_GDSC 8
|
||||
#define USB30_MP_GDSC 9
|
||||
#define USB30_PRIM_GDSC 10
|
||||
#define USB30_SEC_GDSC 11
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
|
||||
|
||||
/* LPASS_AUDIO_CC clocks */
|
||||
#define LPASS_AUDIO_CC_PLL 0
|
||||
#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
|
||||
#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
|
||||
#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
|
||||
#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
|
||||
#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
|
||||
#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
|
||||
#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
|
||||
#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
|
||||
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
|
||||
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
|
||||
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
|
||||
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
|
||||
#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
|
||||
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
|
||||
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
|
||||
|
||||
/* LPASS_AON_CC clocks */
|
||||
#define LPASS_AON_CC_PLL 0
|
||||
#define LPASS_AON_CC_PLL_OUT_EVEN 1
|
||||
#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
|
||||
#define LPASS_AON_CC_PLL_OUT_ODD 3
|
||||
#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
|
||||
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
|
||||
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
|
||||
#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
|
||||
#define LPASS_AON_CC_TX_MCLK_CLK 8
|
||||
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
|
||||
#define LPASS_AON_CC_VA_MEM0_CLK 10
|
||||
|
||||
/* LPASS_AON_CC power domains */
|
||||
#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
|
||||
|
||||
/* LPASS_CORE_CC clocks */
|
||||
#define LPASS_CORE_CC_DIG_PLL 0
|
||||
#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1
|
||||
#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2
|
||||
#define LPASS_CORE_CC_CORE_CLK 3
|
||||
#define LPASS_CORE_CC_CORE_CLK_SRC 4
|
||||
#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5
|
||||
#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6
|
||||
#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7
|
||||
#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8
|
||||
#define LPASS_CORE_CC_LPM_CORE_CLK 9
|
||||
#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
|
||||
#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
|
||||
|
||||
/* LPASS_CORE_CC power domains */
|
||||
#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue