dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230209143702.44408-3-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jianlong Huang
Linus Walleij
parent
d6e0a66009
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 AON Pin Controller
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description: |
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Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
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Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
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can be multiplexed and have configurable bias, drive strength,
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schmitt trigger etc.
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Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
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maintainers:
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- Jianlong Huang <jianlong.huang@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-aon-pinctrl
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reg:
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maxItems: 1
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resets:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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gpio-controller: true
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'#gpio-cells':
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const: 2
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patternProperties:
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'-[0-9]+$':
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type: object
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additionalProperties: false
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patternProperties:
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'-pins$':
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type: object
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description: |
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A pinctrl node should contain at least one subnode representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to
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muxer configuration, bias, input enable/disable, input schmitt
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trigger enable/disable, slew-rate and drive strength.
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allOf:
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- $ref: /schemas/pinctrl/pincfg-node.yaml
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- $ref: /schemas/pinctrl/pinmux-node.yaml
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additionalProperties: false
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properties:
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pinmux:
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description: |
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The list of GPIOs and their mux settings that properties in the
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node apply to. This should be set using the GPIOMUX macro.
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bias-disable: true
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bias-pull-up:
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type: boolean
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bias-pull-down:
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type: boolean
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drive-strength:
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enum: [ 2, 4, 8, 12 ]
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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slew-rate:
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maximum: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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additionalProperties: false
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examples:
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- |
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pinctrl@17020000 {
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compatible = "starfive,jh7110-aon-pinctrl";
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reg = <0x17020000 0x10000>;
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resets = <&aoncrg 2>;
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interrupts = <85>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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pwm-0 {
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pwm-pins {
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pinmux = <0xff030802>;
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bias-disable;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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};
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...
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@ -104,6 +104,28 @@
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#define PAD_QSPI_DATA2 93
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#define PAD_QSPI_DATA3 94
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/* aon_iomux pins */
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#define PAD_TESTEN 0
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#define PAD_RGPIO0 1
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#define PAD_RGPIO1 2
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#define PAD_RGPIO2 3
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#define PAD_RGPIO3 4
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#define PAD_RSTN 5
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#define PAD_GMAC0_MDC 6
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#define PAD_GMAC0_MDIO 7
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#define PAD_GMAC0_RXD0 8
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#define PAD_GMAC0_RXD1 9
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#define PAD_GMAC0_RXD2 10
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#define PAD_GMAC0_RXD3 11
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#define PAD_GMAC0_RXDV 12
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#define PAD_GMAC0_RXC 13
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#define PAD_GMAC0_TXD0 14
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#define PAD_GMAC0_TXD1 15
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#define PAD_GMAC0_TXD2 16
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#define PAD_GMAC0_TXD3 17
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#define PAD_GMAC0_TXEN 18
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#define PAD_GMAC0_TXC 19
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#define GPOUT_LOW 0
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#define GPOUT_HIGH 1
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