clk: mediatek: Add MT6779 clock support
Add MT6779 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: mtk01761 <wendell.lin@mediatek.com> Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
mtk01761
Stephen Boyd
parent
85b18fe704
commit
710774e048
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@ -117,6 +117,62 @@ config COMMON_CLK_MT2712_VENCSYS
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---help---
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This driver supports MediaTek MT2712 vencsys clocks.
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config COMMON_CLK_MT6779
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bool "Clock driver for MediaTek MT6779"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK && ARM64
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help
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This driver supports MediaTek MT6779 basic clocks.
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config COMMON_CLK_MT6779_MMSYS
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bool "Clock driver for MediaTek MT6779 mmsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 mmsys clocks.
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config COMMON_CLK_MT6779_IMGSYS
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bool "Clock driver for MediaTek MT6779 imgsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 imgsys clocks.
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config COMMON_CLK_MT6779_IPESYS
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bool "Clock driver for MediaTek MT6779 ipesys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 ipesys clocks.
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config COMMON_CLK_MT6779_CAMSYS
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bool "Clock driver for MediaTek MT6779 camsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 camsys clocks.
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config COMMON_CLK_MT6779_VDECSYS
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bool "Clock driver for MediaTek MT6779 vdecsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 vdecsys clocks.
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config COMMON_CLK_MT6779_VENCSYS
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bool "Clock driver for MediaTek MT6779 vencsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 vencsys clocks.
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config COMMON_CLK_MT6779_MFGCFG
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bool "Clock driver for MediaTek MT6779 mfgcfg"
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depends on COMMON_CLK_MT6779
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help
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This driver supports MediaTek MT6779 mfgcfg clocks.
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config COMMON_CLK_MT6779_AUDSYS
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bool "Clock driver for Mediatek MT6779 audsys"
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depends on COMMON_CLK_MT6779
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help
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This driver supports Mediatek MT6779 audsys clocks.
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config COMMON_CLK_MT6797
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bool "Clock driver for MediaTek MT6797"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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@ -1,6 +1,15 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
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obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
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obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
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obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
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obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
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obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
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obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
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obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
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obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
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obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
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obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
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@ -0,0 +1,117 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6779-clk.h>
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static const struct mtk_gate_regs audio0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audio1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x4,
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.sta_ofs = 0x4,
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};
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#define GATE_AUDIO0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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#define GATE_AUDIO1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate audio_clks[] = {
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/* AUDIO0 */
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GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
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GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
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GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
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GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
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"aud_eng2_sel", 18),
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GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
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"aud_eng1_sel", 19),
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GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
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GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
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GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
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GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
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"audio_sel", 26),
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GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
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GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
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/* AUDIO1 */
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GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
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"audio_sel", 4),
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GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
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"audio_sel", 5),
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GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
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"audio_sel", 6),
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GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
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"audio_sel", 7),
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GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
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"audio_sel", 8),
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GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
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"audio_sel", 12),
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GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
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"audio_sel", 13),
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GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
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"audio_sel", 14),
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GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
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"audio_h_sel", 15),
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GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
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"audio_h_sel", 16),
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GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
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"audio_h_sel", 17),
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GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
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"audio_sel", 20),
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GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
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"audio_h_sel",
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21),
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GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
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28),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
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"audio_sel", 29),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
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"audio_sel", 30),
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GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
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"audio_h_sel", 31),
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};
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static const struct of_device_id of_match_clk_mt6779_aud[] = {
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{ .compatible = "mediatek,mt6779-audio", },
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{}
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};
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static int clk_mt6779_aud_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
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mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static struct platform_driver clk_mt6779_aud_drv = {
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.probe = clk_mt6779_aud_probe,
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.driver = {
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.name = "clk-mt6779-aud",
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.of_match_table = of_match_clk_mt6779_aud,
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},
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};
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builtin_platform_driver(clk_mt6779_aud_drv);
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@ -0,0 +1,66 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt6779-clk.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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static const struct mtk_gate_regs cam_cg_regs = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_CAM(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate cam_clks[] = {
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GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
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GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
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GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
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GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
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GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
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GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
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GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
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GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
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GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
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GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
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GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
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GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
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GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
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};
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static const struct of_device_id of_match_clk_mt6779_cam[] = {
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{ .compatible = "mediatek,mt6779-camsys", },
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{}
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};
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static int clk_mt6779_cam_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
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mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static struct platform_driver clk_mt6779_cam_drv = {
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.probe = clk_mt6779_cam_probe,
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.driver = {
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.name = "clk-mt6779-cam",
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.of_match_table = of_match_clk_mt6779_cam,
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},
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};
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builtin_platform_driver(clk_mt6779_cam_drv);
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt6779-clk.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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static const struct mtk_gate_regs img_cg_regs = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_IMG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate img_clks[] = {
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GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
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GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
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GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
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GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
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GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
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};
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static const struct of_device_id of_match_clk_mt6779_img[] = {
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{ .compatible = "mediatek,mt6779-imgsys", },
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{}
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};
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static int clk_mt6779_img_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
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mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static struct platform_driver clk_mt6779_img_drv = {
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.probe = clk_mt6779_img_probe,
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.driver = {
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.name = "clk-mt6779-img",
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.of_match_table = of_match_clk_mt6779_img,
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},
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};
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builtin_platform_driver(clk_mt6779_img_drv);
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@ -0,0 +1,60 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt6779-clk.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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static const struct mtk_gate_regs ipe_cg_regs = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_IPE(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate ipe_clks[] = {
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GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
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GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
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GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
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GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
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GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
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GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
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GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
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};
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static const struct of_device_id of_match_clk_mt6779_ipe[] = {
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{ .compatible = "mediatek,mt6779-ipesys", },
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{}
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};
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static int clk_mt6779_ipe_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
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mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static struct platform_driver clk_mt6779_ipe_drv = {
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||||
.probe = clk_mt6779_ipe_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-ipe",
|
||||
.of_match_table = of_match_clk_mt6779_ipe,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6779_ipe_drv);
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: Wendell Lin <wendell.lin@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6779-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mfg_clks[] = {
|
||||
GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
|
||||
};
|
||||
|
||||
static int clk_mt6779_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779_mfg[] = {
|
||||
{ .compatible = "mediatek,mt6779-mfgcfg", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt6779_mfg_drv = {
|
||||
.probe = clk_mt6779_mfg_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-mfg",
|
||||
.of_match_table = of_match_clk_mt6779_mfg,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6779_mfg_drv);
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: Wendell Lin <wendell.lin@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt6779-clk.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
static const struct mtk_gate_regs mm0_cg_regs = {
|
||||
.set_ofs = 0x0104,
|
||||
.clr_ofs = 0x0108,
|
||||
.sta_ofs = 0x0100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm1_cg_regs = {
|
||||
.set_ofs = 0x0114,
|
||||
.clr_ofs = 0x0118,
|
||||
.sta_ofs = 0x0110,
|
||||
};
|
||||
|
||||
#define GATE_MM0(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr)
|
||||
#define GATE_MM1(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM0 */
|
||||
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
|
||||
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
||||
GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
|
||||
GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
|
||||
GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
|
||||
GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
|
||||
GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
|
||||
GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
|
||||
GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
|
||||
GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
|
||||
GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
|
||||
GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
|
||||
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
|
||||
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
|
||||
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
|
||||
GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
|
||||
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
|
||||
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
|
||||
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
|
||||
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
|
||||
GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
|
||||
/* MM1 */
|
||||
GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
|
||||
GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
|
||||
GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
|
||||
GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
|
||||
GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
|
||||
GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
|
||||
GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
|
||||
GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
|
||||
GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
|
||||
GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
|
||||
GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
|
||||
GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
|
||||
GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
|
||||
GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
|
||||
GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
|
||||
GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
|
||||
GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779_mm[] = {
|
||||
{ .compatible = "mediatek,mt6779-mmsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt6779_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_mm_drv = {
|
||||
.probe = clk_mt6779_mm_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-mm",
|
||||
.of_match_table = of_match_clk_mt6779_mm,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6779_mm_drv);
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: Wendell Lin <wendell.lin@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6779-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs vdec0_cg_regs = {
|
||||
.set_ofs = 0x0000,
|
||||
.clr_ofs = 0x0004,
|
||||
.sta_ofs = 0x0000,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs vdec1_cg_regs = {
|
||||
.set_ofs = 0x0008,
|
||||
.clr_ofs = 0x000c,
|
||||
.sta_ofs = 0x0008,
|
||||
};
|
||||
|
||||
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr_inv)
|
||||
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr_inv)
|
||||
|
||||
static const struct mtk_gate vdec_clks[] = {
|
||||
/* VDEC0 */
|
||||
GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
|
||||
/* VDEC1 */
|
||||
GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779_vdec[] = {
|
||||
{ .compatible = "mediatek,mt6779-vdecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt6779_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_vdec_drv = {
|
||||
.probe = clk_mt6779_vdec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-vdec",
|
||||
.of_match_table = of_match_clk_mt6779_vdec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6779_vdec_drv);
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: Wendell Lin <wendell.lin@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt6779-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs venc_cg_regs = {
|
||||
.set_ofs = 0x0004,
|
||||
.clr_ofs = 0x0008,
|
||||
.sta_ofs = 0x0000,
|
||||
};
|
||||
|
||||
#define GATE_VENC_I(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr_inv)
|
||||
|
||||
static const struct mtk_gate venc_clks[] = {
|
||||
GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
|
||||
GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
|
||||
GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
|
||||
GATE_VENC_I(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779_venc[] = {
|
||||
{ .compatible = "mediatek,mt6779-vencsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt6779_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_venc_drv = {
|
||||
.probe = clk_mt6779_venc_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-venc",
|
||||
.of_match_table = of_match_clk_mt6779_venc,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt6779_venc_drv);
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue