ARM: integrator: Delete the V3 PCI driver
Before adding a proper PCI driver in drivers/pci/host, clean out the cruft by deleting the old driver from the machine. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
2bd6bf03f4
commit
70f8e9cc23
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@ -7,6 +7,4 @@
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obj-y := core.o lm.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
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obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
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obj-$(CONFIG_PCI) += pci_v3.o
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obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
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@ -36,7 +36,6 @@
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#include "hardware.h"
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#include "cm.h"
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#include "common.h"
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#include "pci_v3.h"
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#include "lm.h"
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/* Regmap to the AP system controller */
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@ -74,7 +73,6 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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pci_v3_early_init();
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}
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#ifdef CONFIG_PM
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@ -1,900 +0,0 @@
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/*
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* linux/arch/arm/mach-integrator/pci_v3.c
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*
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* PCI functions for V3 host PCI bridge
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <video/vga.h>
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#include <asm/mach/map.h>
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#include <asm/signal.h>
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#include <asm/mach/pci.h>
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#include <asm/irq_regs.h>
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#include "pci_v3.h"
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#include "hardware.h"
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/*
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* Where in the memory map does PCI live?
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*
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* This represents a fairly liberal usage of address space. Even though
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* the V3 only has two windows (therefore we need to map stuff on the fly),
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* we maintain the same addresses, even if they're not mapped.
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*/
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#define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */
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#define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */
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#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
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#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
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#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
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#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
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#define PCI_CONFIG_VADDR IOMEM(0xec000000)
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/*
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* V3 Local Bus to PCI Bridge definitions
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*
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* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
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* All V3 register names are prefaced by V3_ to avoid clashing with any other
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* PCI definitions. Their names match the user's manual.
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*
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* I'm assuming that I20 is disabled.
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*
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*/
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#define V3_PCI_VENDOR 0x00000000
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#define V3_PCI_DEVICE 0x00000002
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#define V3_PCI_CMD 0x00000004
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#define V3_PCI_STAT 0x00000006
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#define V3_PCI_CC_REV 0x00000008
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#define V3_PCI_HDR_CFG 0x0000000C
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#define V3_PCI_IO_BASE 0x00000010
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#define V3_PCI_BASE0 0x00000014
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#define V3_PCI_BASE1 0x00000018
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#define V3_PCI_SUB_VENDOR 0x0000002C
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#define V3_PCI_SUB_ID 0x0000002E
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#define V3_PCI_ROM 0x00000030
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#define V3_PCI_BPARAM 0x0000003C
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#define V3_PCI_MAP0 0x00000040
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#define V3_PCI_MAP1 0x00000044
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#define V3_PCI_INT_STAT 0x00000048
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#define V3_PCI_INT_CFG 0x0000004C
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#define V3_LB_BASE0 0x00000054
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#define V3_LB_BASE1 0x00000058
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#define V3_LB_MAP0 0x0000005E
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#define V3_LB_MAP1 0x00000062
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#define V3_LB_BASE2 0x00000064
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#define V3_LB_MAP2 0x00000066
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#define V3_LB_SIZE 0x00000068
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#define V3_LB_IO_BASE 0x0000006E
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#define V3_FIFO_CFG 0x00000070
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#define V3_FIFO_PRIORITY 0x00000072
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#define V3_FIFO_STAT 0x00000074
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#define V3_LB_ISTAT 0x00000076
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#define V3_LB_IMASK 0x00000077
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#define V3_SYSTEM 0x00000078
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#define V3_LB_CFG 0x0000007A
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#define V3_PCI_CFG 0x0000007C
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#define V3_DMA_PCI_ADR0 0x00000080
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#define V3_DMA_PCI_ADR1 0x00000090
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#define V3_DMA_LOCAL_ADR0 0x00000084
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#define V3_DMA_LOCAL_ADR1 0x00000094
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#define V3_DMA_LENGTH0 0x00000088
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#define V3_DMA_LENGTH1 0x00000098
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#define V3_DMA_CSR0 0x0000008B
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#define V3_DMA_CSR1 0x0000009B
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#define V3_DMA_CTLB_ADR0 0x0000008C
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#define V3_DMA_CTLB_ADR1 0x0000009C
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#define V3_DMA_DELAY 0x000000E0
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#define V3_MAIL_DATA 0x000000C0
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#define V3_PCI_MAIL_IEWR 0x000000D0
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#define V3_PCI_MAIL_IERD 0x000000D2
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#define V3_LB_MAIL_IEWR 0x000000D4
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#define V3_LB_MAIL_IERD 0x000000D6
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#define V3_MAIL_WR_STAT 0x000000D8
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#define V3_MAIL_RD_STAT 0x000000DA
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#define V3_QBA_MAP 0x000000DC
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/* PCI COMMAND REGISTER bits
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*/
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#define V3_COMMAND_M_FBB_EN (1 << 9)
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#define V3_COMMAND_M_SERR_EN (1 << 8)
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#define V3_COMMAND_M_PAR_EN (1 << 6)
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#define V3_COMMAND_M_MASTER_EN (1 << 2)
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#define V3_COMMAND_M_MEM_EN (1 << 1)
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#define V3_COMMAND_M_IO_EN (1 << 0)
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/* SYSTEM REGISTER bits
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*/
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#define V3_SYSTEM_M_RST_OUT (1 << 15)
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#define V3_SYSTEM_M_LOCK (1 << 14)
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/* PCI_CFG bits
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*/
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#define V3_PCI_CFG_M_I2O_EN (1 << 15)
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#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
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#define V3_PCI_CFG_M_IO_DIS (1 << 13)
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#define V3_PCI_CFG_M_EN3V (1 << 12)
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
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/* PCI_BASE register bits (PCI -> Local Bus)
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*/
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#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
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#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
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#define V3_PCI_BASE_M_PREFETCH (1 << 3)
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#define V3_PCI_BASE_M_TYPE (3 << 1)
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#define V3_PCI_BASE_M_IO (1 << 0)
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/* PCI MAP register bits (PCI -> Local bus)
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*/
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
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#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
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#define V3_PCI_MAP_M_SWAP (3 << 8)
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
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#define V3_PCI_MAP_M_REG_EN (1 << 1)
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#define V3_PCI_MAP_M_ENABLE (1 << 0)
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/*
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* LB_BASE0,1 register bits (Local bus -> PCI)
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*/
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#define V3_LB_BASE_ADR_BASE 0xfff00000
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#define V3_LB_BASE_SWAP (3 << 8)
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#define V3_LB_BASE_ADR_SIZE (15 << 4)
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#define V3_LB_BASE_PREFETCH (1 << 3)
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#define V3_LB_BASE_ENABLE (1 << 0)
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#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
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#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
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#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
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#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
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#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
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#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
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#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
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#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
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#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
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#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
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#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
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#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
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#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
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/*
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* LB_MAP0,1 register bits (Local bus -> PCI)
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*/
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#define V3_LB_MAP_MAP_ADR 0xfff0
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#define V3_LB_MAP_TYPE (7 << 1)
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#define V3_LB_MAP_AD_LOW_EN (1 << 0)
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#define V3_LB_MAP_TYPE_IACK (0 << 1)
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#define V3_LB_MAP_TYPE_IO (1 << 1)
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#define V3_LB_MAP_TYPE_MEM (3 << 1)
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#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
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#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
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#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
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/*
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* LB_BASE2 register bits (Local bus -> PCI IO)
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*/
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#define V3_LB_BASE2_ADR_BASE 0xff00
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#define V3_LB_BASE2_SWAP (3 << 6)
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#define V3_LB_BASE2_ENABLE (1 << 0)
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#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
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/*
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* LB_MAP2 register bits (Local bus -> PCI IO)
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*/
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#define V3_LB_MAP2_MAP_ADR 0xff00
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#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
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/*
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* The V3 PCI interface chip in Integrator provides several windows from
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* local bus memory into the PCI memory areas. Unfortunately, there
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* are not really enough windows for our usage, therefore we reuse
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* one of the windows for access to PCI configuration space. The
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* memory map is as follows:
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*
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* Local Bus Memory Usage
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*
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* 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
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* 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
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* 60000000 - 60FFFFFF PCI IO. 16M
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* 61000000 - 61FFFFFF PCI Configuration. 16M
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*
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* There are three V3 windows, each described by a pair of V3 registers.
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* These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
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* Base0 and Base1 can be used for any type of PCI memory access. Base2
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* can be used either for PCI I/O or for I20 accesses. By default, uHAL
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* uses this only for PCI IO space.
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*
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* Normally these spaces are mapped using the following base registers:
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*
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* Usage Local Bus Memory Base/Map registers used
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*
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* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
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* Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
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* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
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* Cfg 61000000 - 61FFFFFF
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*
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* This means that I20 and PCI configuration space accesses will fail.
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* When PCI configuration accesses are needed (via the uHAL PCI
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* configuration space primitives) we must remap the spaces as follows:
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*
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* Usage Local Bus Memory Base/Map registers used
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*
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* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
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* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
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* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
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* Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
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*
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* To make this work, the code depends on overlapping windows working.
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* The V3 chip translates an address by checking its range within
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* each of the BASE/MAP pairs in turn (in ascending register number
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* order). It will use the first matching pair. So, for example,
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* if the same address is mapped by both LB_BASE0/LB_MAP0 and
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* LB_BASE1/LB_MAP1, the V3 will use the translation from
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* LB_BASE0/LB_MAP0.
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*
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* To allow PCI Configuration space access, the code enlarges the
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* window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
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* the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
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* be remapped for use by configuration cycles.
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*
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* At the end of the PCI Configuration space accesses,
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* LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
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* mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
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* reveal the now restored LB_BASE1/LB_MAP1 window.
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*
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* NOTE: We do not set up I2O mapping. I suspect that this is only
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* for an intelligent (target) device. Using I2O disables most of
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* the mappings into PCI memory.
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*/
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/* Filled in by probe */
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static void __iomem *pci_v3_base;
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/* CPU side memory ranges */
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static struct resource conf_mem; /* FIXME: remap this instead of static map */
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static struct resource io_mem;
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static struct resource non_mem;
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static struct resource pre_mem;
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/* PCI side memory ranges */
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static u64 non_mem_pci;
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static u64 non_mem_pci_sz;
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static u64 pre_mem_pci;
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static u64 pre_mem_pci_sz;
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// V3 access routines
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#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
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#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
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#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
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#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
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#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
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#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
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/*============================================================================
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*
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* routine: uHALir_PCIMakeConfigAddress()
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*
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* parameters: bus = which bus
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* device = which device
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* function = which function
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* offset = configuration space register we are interested in
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*
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* description: this routine will generate a platform dependent config
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* address.
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*
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* calls: none
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*
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* returns: configuration address to play on the PCI bus
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*
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* To generate the appropriate PCI configuration cycles in the PCI
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* configuration address space, you present the V3 with the following pattern
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* (which is very nearly a type 1 (except that the lower two bits are 00 and
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* not 01). In order for this mapping to work you need to set up one of
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* the local to PCI aperatures to 16Mbytes in length translating to
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* PCI configuration space starting at 0x0000.0000.
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*
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* PCI configuration cycles look like this:
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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*/
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#undef V3_LB_BASE_PREFETCH
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#define V3_LB_BASE_PREFETCH 0
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|
||||
static void __iomem *v3_open_config_window(struct pci_bus *bus,
|
||||
unsigned int devfn, int offset)
|
||||
{
|
||||
unsigned int address, mapaddress, busnr;
|
||||
|
||||
busnr = bus->number;
|
||||
|
||||
/*
|
||||
* Trap out illegal values
|
||||
*/
|
||||
BUG_ON(offset > 255);
|
||||
BUG_ON(busnr > 255);
|
||||
BUG_ON(devfn > 255);
|
||||
|
||||
if (busnr == 0) {
|
||||
int slot = PCI_SLOT(devfn);
|
||||
|
||||
/*
|
||||
* local bus segment so need a type 0 config cycle
|
||||
*
|
||||
* build the PCI configuration "address" with one-hot in
|
||||
* A31-A11
|
||||
*
|
||||
* mapaddress:
|
||||
* 3:1 = config cycle (101)
|
||||
* 0 = PCI A1 & A0 are 0 (0)
|
||||
*/
|
||||
address = PCI_FUNC(devfn) << 8;
|
||||
mapaddress = V3_LB_MAP_TYPE_CONFIG;
|
||||
|
||||
if (slot > 12)
|
||||
/*
|
||||
* high order bits are handled by the MAP register
|
||||
*/
|
||||
mapaddress |= 1 << (slot - 5);
|
||||
else
|
||||
/*
|
||||
* low order bits handled directly in the address
|
||||
*/
|
||||
address |= 1 << (slot + 11);
|
||||
} else {
|
||||
/*
|
||||
* not the local bus segment so need a type 1 config cycle
|
||||
*
|
||||
* address:
|
||||
* 23:16 = bus number
|
||||
* 15:11 = slot number (7:3 of devfn)
|
||||
* 10:8 = func number (2:0 of devfn)
|
||||
*
|
||||
* mapaddress:
|
||||
* 3:1 = config cycle (101)
|
||||
* 0 = PCI A1 & A0 from host bus (1)
|
||||
*/
|
||||
mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
|
||||
address = (busnr << 16) | (devfn << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up base0 to see all 512Mbytes of memory space (not
|
||||
* prefetchable), this frees up base1 for re-use by
|
||||
* configuration memory
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
|
||||
|
||||
/*
|
||||
* Set up base1/map1 to point into configuration space.
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, mapaddress);
|
||||
|
||||
return PCI_CONFIG_VADDR + address + offset;
|
||||
}
|
||||
|
||||
static void v3_close_config_window(void)
|
||||
{
|
||||
/*
|
||||
* Reassign base1 for use by prefetchable PCI memory
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
|
||||
V3_LB_MAP_TYPE_MEM_MULTIPLE);
|
||||
|
||||
/*
|
||||
* And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
|
||||
}
|
||||
|
||||
static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
int size, u32 *val)
|
||||
{
|
||||
int ret = pci_generic_config_read(bus, devfn, where, size, val);
|
||||
v3_close_config_window();
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
int size, u32 val)
|
||||
{
|
||||
int ret = pci_generic_config_write(bus, devfn, where, size, val);
|
||||
v3_close_config_window();
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct pci_ops pci_v3_ops = {
|
||||
.map_bus = v3_open_config_window,
|
||||
.read = v3_read_config,
|
||||
.write = v3_write_config,
|
||||
};
|
||||
|
||||
static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
|
||||
{
|
||||
if (request_resource(&iomem_resource, &non_mem)) {
|
||||
printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
|
||||
"memory region\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
if (request_resource(&iomem_resource, &pre_mem)) {
|
||||
release_resource(&non_mem);
|
||||
printk(KERN_ERR "PCI: unable to allocate prefetchable "
|
||||
"memory region\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/*
|
||||
* the mem resource for this bus
|
||||
* the prefetch mem resource for this bus
|
||||
*/
|
||||
pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
|
||||
pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* These don't seem to be implemented on the Integrator I have, which
|
||||
* means I can't get additional information on the reason for the pm2fb
|
||||
* problems. I suppose I'll just have to mind-meld with the machine. ;)
|
||||
*/
|
||||
static void __iomem *ap_syscon_base;
|
||||
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
|
||||
#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
|
||||
#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
|
||||
|
||||
static int
|
||||
v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
|
||||
{
|
||||
unsigned long pc = instruction_pointer(regs);
|
||||
unsigned long instr = *(unsigned long *)pc;
|
||||
#if 0
|
||||
char buf[128];
|
||||
|
||||
sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
|
||||
addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
|
||||
v3_readb(V3_LB_ISTAT));
|
||||
printk(KERN_DEBUG "%s", buf);
|
||||
#endif
|
||||
|
||||
v3_writeb(V3_LB_ISTAT, 0);
|
||||
__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
|
||||
|
||||
/*
|
||||
* If the instruction being executed was a read,
|
||||
* make it look like it read all-ones.
|
||||
*/
|
||||
if ((instr & 0x0c100000) == 0x04100000) {
|
||||
int reg = (instr >> 12) & 15;
|
||||
unsigned long val;
|
||||
|
||||
if (instr & 0x00400000)
|
||||
val = 255;
|
||||
else
|
||||
val = -1;
|
||||
|
||||
regs->uregs[reg] = val;
|
||||
regs->ARM_pc += 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((instr & 0x0e100090) == 0x00100090) {
|
||||
int reg = (instr >> 12) & 15;
|
||||
|
||||
regs->uregs[reg] = -1;
|
||||
regs->ARM_pc += 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static irqreturn_t v3_irq(int irq, void *devid)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
struct pt_regs *regs = get_irq_regs();
|
||||
unsigned long pc = instruction_pointer(regs);
|
||||
unsigned long instr = *(unsigned long *)pc;
|
||||
char buf[128];
|
||||
extern void printascii(const char *);
|
||||
|
||||
sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
|
||||
"ISTAT=%02x\n", irq, pc, instr,
|
||||
__raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
|
||||
__raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
|
||||
v3_readb(V3_LB_ISTAT));
|
||||
printascii(buf);
|
||||
#endif
|
||||
|
||||
v3_writew(V3_PCI_STAT, 0xf000);
|
||||
v3_writeb(V3_LB_ISTAT, 0);
|
||||
__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
|
||||
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
/*
|
||||
* If the instruction being executed was a read,
|
||||
* make it look like it read all-ones.
|
||||
*/
|
||||
if ((instr & 0x0c100000) == 0x04100000) {
|
||||
int reg = (instr >> 16) & 15;
|
||||
sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
|
||||
printascii(buf);
|
||||
}
|
||||
#endif
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!ap_syscon_base)
|
||||
return -EINVAL;
|
||||
|
||||
if (nr == 0) {
|
||||
sys->mem_offset = non_mem.start;
|
||||
ret = pci_v3_setup_resources(sys);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* V3_LB_BASE? - local bus address
|
||||
* V3_LB_MAP? - pci bus address
|
||||
*/
|
||||
static void __init pci_v3_preinit(void)
|
||||
{
|
||||
unsigned int temp;
|
||||
phys_addr_t io_address = pci_pio_to_address(io_mem.start);
|
||||
|
||||
pcibios_min_mem = 0x00100000;
|
||||
|
||||
/*
|
||||
* Hook in our fault handler for PCI errors
|
||||
*/
|
||||
hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
|
||||
hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
|
||||
hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
|
||||
hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
|
||||
|
||||
/*
|
||||
* Unlock V3 registers, but only if they were previously locked.
|
||||
*/
|
||||
if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
|
||||
v3_writew(V3_SYSTEM, 0xa05f);
|
||||
|
||||
/*
|
||||
* Setup window 0 - PCI non-prefetchable memory
|
||||
* Local: 0x40000000 Bus: 0x00000000 Size: 256MB
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
|
||||
V3_LB_MAP_TYPE_MEM);
|
||||
|
||||
/*
|
||||
* Setup window 1 - PCI prefetchable memory
|
||||
* Local: 0x50000000 Bus: 0x10000000 Size: 256MB
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
|
||||
V3_LB_MAP_TYPE_MEM_MULTIPLE);
|
||||
|
||||
/*
|
||||
* Setup window 2 - PCI IO
|
||||
*/
|
||||
v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
|
||||
|
||||
/*
|
||||
* Disable PCI to host IO cycles
|
||||
*/
|
||||
temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
|
||||
temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
|
||||
v3_writew(V3_PCI_CFG, temp);
|
||||
|
||||
printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
|
||||
v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
|
||||
|
||||
/*
|
||||
* Set the V3 FIFO such that writes have higher priority than
|
||||
* reads, and local bus write causes local bus read fifo flush.
|
||||
* Same for PCI.
|
||||
*/
|
||||
v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
|
||||
|
||||
/*
|
||||
* Re-lock the system register.
|
||||
*/
|
||||
temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
|
||||
v3_writew(V3_SYSTEM, temp);
|
||||
|
||||
/*
|
||||
* Clear any error conditions, and enable write errors.
|
||||
*/
|
||||
v3_writeb(V3_LB_ISTAT, 0);
|
||||
v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
|
||||
v3_writeb(V3_LB_IMASK, 0x28);
|
||||
__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
|
||||
}
|
||||
|
||||
static void __init pci_v3_postinit(void)
|
||||
{
|
||||
unsigned int pci_cmd;
|
||||
phys_addr_t io_address = pci_pio_to_address(io_mem.start);
|
||||
|
||||
pci_cmd = PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
|
||||
|
||||
v3_writew(V3_PCI_CMD, pci_cmd);
|
||||
|
||||
v3_writeb(V3_LB_ISTAT, ~0x40);
|
||||
v3_writeb(V3_LB_IMASK, 0x68);
|
||||
|
||||
#if 0
|
||||
ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
|
||||
if (ret)
|
||||
printk(KERN_ERR "PCI: unable to grab local bus timeout "
|
||||
"interrupt: %d\n", ret);
|
||||
#endif
|
||||
|
||||
register_isa_ports(non_mem.start, io_address, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* A small note about bridges and interrupts. The DECchip 21050 (and
|
||||
* later) adheres to the PCI-PCI bridge specification. This says that
|
||||
* the interrupts on the other side of a bridge are swizzled in the
|
||||
* following manner:
|
||||
*
|
||||
* Dev Interrupt Interrupt
|
||||
* Pin on Pin on
|
||||
* Device Connector
|
||||
*
|
||||
* 4 A A
|
||||
* B B
|
||||
* C C
|
||||
* D D
|
||||
*
|
||||
* 5 A B
|
||||
* B C
|
||||
* C D
|
||||
* D A
|
||||
*
|
||||
* 6 A C
|
||||
* B D
|
||||
* C A
|
||||
* D B
|
||||
*
|
||||
* 7 A D
|
||||
* B A
|
||||
* C B
|
||||
* D C
|
||||
*
|
||||
* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
|
||||
* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
|
||||
*/
|
||||
|
||||
/*
|
||||
* This routine handles multiple bridges.
|
||||
*/
|
||||
static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
{
|
||||
if (*pinp == 0)
|
||||
*pinp = 1;
|
||||
|
||||
return pci_common_swizzle(dev, pinp);
|
||||
}
|
||||
|
||||
static struct hw_pci pci_v3 __initdata = {
|
||||
.swizzle = pci_v3_swizzle,
|
||||
.setup = pci_v3_setup,
|
||||
.nr_controllers = 1,
|
||||
.ops = &pci_v3_ops,
|
||||
.preinit = pci_v3_preinit,
|
||||
.postinit = pci_v3_postinit,
|
||||
};
|
||||
|
||||
static int __init pci_v3_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct of_pci_range_parser parser;
|
||||
struct of_pci_range range;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
|
||||
/* Remap the Integrator system controller */
|
||||
ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100);
|
||||
if (!ap_syscon_base) {
|
||||
dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Device tree probe path */
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "no device tree node for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_pci_range_parser_init(&parser, np))
|
||||
return -EINVAL;
|
||||
|
||||
/* Get base for bridge registers */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
pci_v3_base = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!pci_v3_base) {
|
||||
dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Get and request error IRQ resource */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
|
||||
"PCIv3 error", NULL);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
if (!range.flags) {
|
||||
ret = of_pci_range_to_resource(&range, np, &conf_mem);
|
||||
conf_mem.name = "PCIv3 config";
|
||||
}
|
||||
if (range.flags & IORESOURCE_IO) {
|
||||
ret = of_pci_range_to_resource(&range, np, &io_mem);
|
||||
io_mem.name = "PCIv3 I/O";
|
||||
}
|
||||
if ((range.flags & IORESOURCE_MEM) &&
|
||||
!(range.flags & IORESOURCE_PREFETCH)) {
|
||||
non_mem_pci = range.pci_addr;
|
||||
non_mem_pci_sz = range.size;
|
||||
ret = of_pci_range_to_resource(&range, np, &non_mem);
|
||||
non_mem.name = "PCIv3 non-prefetched mem";
|
||||
}
|
||||
if ((range.flags & IORESOURCE_MEM) &&
|
||||
(range.flags & IORESOURCE_PREFETCH)) {
|
||||
pre_mem_pci = range.pci_addr;
|
||||
pre_mem_pci_sz = range.size;
|
||||
ret = of_pci_range_to_resource(&range, np, &pre_mem);
|
||||
pre_mem.name = "PCIv3 prefetched mem";
|
||||
}
|
||||
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "missing ranges in device node\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
pci_v3.map_irq = of_irq_parse_and_map_pci;
|
||||
pci_common_init_dev(&pdev->dev, &pci_v3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pci_ids[] = {
|
||||
{ .compatible = "v3,v360epc-pci", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver pci_v3_driver = {
|
||||
.driver = {
|
||||
.name = "pci-v3",
|
||||
.of_match_table = pci_ids,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init pci_v3_init(void)
|
||||
{
|
||||
return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
|
||||
}
|
||||
|
||||
subsys_initcall(pci_v3_init);
|
||||
|
||||
/*
|
||||
* Static mappings for the PCIv3 bridge
|
||||
*
|
||||
* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
|
||||
* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
|
||||
* fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
|
||||
*/
|
||||
static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
|
||||
{
|
||||
.virtual = (unsigned long)PCI_MEMORY_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = (unsigned long)PCI_CONFIG_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
int __init pci_v3_early_init(void)
|
||||
{
|
||||
iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
|
||||
vga_base = (unsigned long)PCI_MEMORY_VADDR;
|
||||
pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* Simple oneliner include to the PCIv3 early init */
|
||||
#ifdef CONFIG_PCI
|
||||
extern int pci_v3_early_init(void);
|
||||
#else
|
||||
static inline int pci_v3_early_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue