Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
This commit is contained in:
Linus Torvalds
commit
70d9d825e0
|
|
@ -1,48 +1,153 @@
|
|||
S2IO Technologies XFrame 10 Gig adapter.
|
||||
-------------------------------------------
|
||||
Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
|
||||
|
||||
I. Module loadable parameters.
|
||||
When loaded as a module, the driver provides a host of Module loadable
|
||||
parameters, so the device can be tuned as per the users needs.
|
||||
A list of the Module params is given below.
|
||||
(i) ring_num: This can be used to program the number of
|
||||
receive rings used in the driver.
|
||||
(ii) ring_len: This defines the number of descriptors each ring
|
||||
can have. There can be a maximum of 8 rings.
|
||||
(iii) frame_len: This is an array of size 8. Using this we can
|
||||
set the maximum size of the received frame that can
|
||||
be steered into the corrsponding receive ring.
|
||||
(iv) fifo_num: This defines the number of Tx FIFOs thats used in
|
||||
the driver.
|
||||
(v) fifo_len: Each element defines the number of
|
||||
Tx descriptors that can be associated with each
|
||||
corresponding FIFO. There are a maximum of 8 FIFOs.
|
||||
(vi) tx_prio: This is a bool, if module is loaded with a non-zero
|
||||
value for tx_prio multi FIFO scheme is activated.
|
||||
(vii) rx_prio: This is a bool, if module is loaded with a non-zero
|
||||
value for tx_prio multi RING scheme is activated.
|
||||
(viii) latency_timer: The value given against this param will be
|
||||
loaded into the latency timer register in PCI Config
|
||||
space, else the register is left with its reset value.
|
||||
Contents
|
||||
=======
|
||||
- 1. Introduction
|
||||
- 2. Identifying the adapter/interface
|
||||
- 3. Features supported
|
||||
- 4. Command line parameters
|
||||
- 5. Performance suggestions
|
||||
- 6. Available Downloads
|
||||
|
||||
II. Performance tuning.
|
||||
By changing a few sysctl parameters.
|
||||
Copy the following lines into a file and run the following command,
|
||||
"sysctl -p <file_name>"
|
||||
### IPV4 specific settings
|
||||
net.ipv4.tcp_timestamps = 0 # turns TCP timestamp support off, default 1, reduces CPU use
|
||||
net.ipv4.tcp_sack = 0 # turn SACK support off, default on
|
||||
# on systems with a VERY fast bus -> memory interface this is the big gainer
|
||||
net.ipv4.tcp_rmem = 10000000 10000000 10000000 # sets min/default/max TCP read buffer, default 4096 87380 174760
|
||||
net.ipv4.tcp_wmem = 10000000 10000000 10000000 # sets min/pressure/max TCP write buffer, default 4096 16384 131072
|
||||
net.ipv4.tcp_mem = 10000000 10000000 10000000 # sets min/pressure/max TCP buffer space, default 31744 32256 32768
|
||||
|
||||
### CORE settings (mostly for socket and UDP effect)
|
||||
net.core.rmem_max = 524287 # maximum receive socket buffer size, default 131071
|
||||
net.core.wmem_max = 524287 # maximum send socket buffer size, default 131071
|
||||
net.core.rmem_default = 524287 # default receive socket buffer size, default 65535
|
||||
net.core.wmem_default = 524287 # default send socket buffer size, default 65535
|
||||
net.core.optmem_max = 524287 # maximum amount of option memory buffers, default 10240
|
||||
net.core.netdev_max_backlog = 300000 # number of unprocessed input packets before kernel starts dropping them, default 300
|
||||
---End of performance tuning file---
|
||||
|
||||
1. Introduction:
|
||||
This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
|
||||
Xframe II PCI-X 2.0 adapters. It supports several features
|
||||
such as jumbo frames, MSI/MSI-X, checksum offloads, TSO, UFO and so on.
|
||||
See below for complete list of features.
|
||||
All features are supported for both IPv4 and IPv6.
|
||||
|
||||
2. Identifying the adapter/interface:
|
||||
a. Insert the adapter(s) in your system.
|
||||
b. Build and load driver
|
||||
# insmod s2io.ko
|
||||
c. View log messages
|
||||
# dmesg | tail -40
|
||||
You will see messages similar to:
|
||||
eth3: Neterion Xframe I 10GbE adapter (rev 3), Version 2.0.9.1, Intr type INTA
|
||||
eth4: Neterion Xframe II 10GbE adapter (rev 2), Version 2.0.9.1, Intr type INTA
|
||||
eth4: Device is on 64 bit 133MHz PCIX(M1) bus
|
||||
|
||||
The above messages identify the adapter type(Xframe I/II), adapter revision,
|
||||
driver version, interface name(eth3, eth4), Interrupt type(INTA, MSI, MSI-X).
|
||||
In case of Xframe II, the PCI/PCI-X bus width and frequency are displayed
|
||||
as well.
|
||||
|
||||
To associate an interface with a physical adapter use "ethtool -p <ethX>".
|
||||
The corresponding adapter's LED will blink multiple times.
|
||||
|
||||
3. Features supported:
|
||||
a. Jumbo frames. Xframe I/II supports MTU upto 9600 bytes,
|
||||
modifiable using ifconfig command.
|
||||
|
||||
b. Offloads. Supports checksum offload(TCP/UDP/IP) on transmit
|
||||
and receive, TSO.
|
||||
|
||||
c. Multi-buffer receive mode. Scattering of packet across multiple
|
||||
buffers. Currently driver supports 2-buffer mode which yields
|
||||
significant performance improvement on certain platforms(SGI Altix,
|
||||
IBM xSeries).
|
||||
|
||||
d. MSI/MSI-X. Can be enabled on platforms which support this feature
|
||||
(IA64, Xeon) resulting in noticeable performance improvement(upto 7%
|
||||
on certain platforms).
|
||||
|
||||
e. NAPI. Compile-time option(CONFIG_S2IO_NAPI) for better Rx interrupt
|
||||
moderation.
|
||||
|
||||
f. Statistics. Comprehensive MAC-level and software statistics displayed
|
||||
using "ethtool -S" option.
|
||||
|
||||
g. Multi-FIFO/Ring. Supports up to 8 transmit queues and receive rings,
|
||||
with multiple steering options.
|
||||
|
||||
4. Command line parameters
|
||||
a. tx_fifo_num
|
||||
Number of transmit queues
|
||||
Valid range: 1-8
|
||||
Default: 1
|
||||
|
||||
b. rx_ring_num
|
||||
Number of receive rings
|
||||
Valid range: 1-8
|
||||
Default: 1
|
||||
|
||||
c. tx_fifo_len
|
||||
Size of each transmit queue
|
||||
Valid range: Total length of all queues should not exceed 8192
|
||||
Default: 4096
|
||||
|
||||
d. rx_ring_sz
|
||||
Size of each receive ring(in 4K blocks)
|
||||
Valid range: Limited by memory on system
|
||||
Default: 30
|
||||
|
||||
e. intr_type
|
||||
Specifies interrupt type. Possible values 1(INTA), 2(MSI), 3(MSI-X)
|
||||
Valid range: 1-3
|
||||
Default: 1
|
||||
|
||||
5. Performance suggestions
|
||||
General:
|
||||
a. Set MTU to maximum(9000 for switch setup, 9600 in back-to-back configuration)
|
||||
b. Set TCP windows size to optimal value.
|
||||
For instance, for MTU=1500 a value of 210K has been observed to result in
|
||||
good performance.
|
||||
# sysctl -w net.ipv4.tcp_rmem="210000 210000 210000"
|
||||
# sysctl -w net.ipv4.tcp_wmem="210000 210000 210000"
|
||||
For MTU=9000, TCP window size of 10 MB is recommended.
|
||||
# sysctl -w net.ipv4.tcp_rmem="10000000 10000000 10000000"
|
||||
# sysctl -w net.ipv4.tcp_wmem="10000000 10000000 10000000"
|
||||
|
||||
Transmit performance:
|
||||
a. By default, the driver respects BIOS settings for PCI bus parameters.
|
||||
However, you may want to experiment with PCI bus parameters
|
||||
max-split-transactions(MOST) and MMRBC (use setpci command).
|
||||
A MOST value of 2 has been found optimal for Opterons and 3 for Itanium.
|
||||
It could be different for your hardware.
|
||||
Set MMRBC to 4K**.
|
||||
|
||||
For example you can set
|
||||
For opteron
|
||||
#setpci -d 17d5:* 62=1d
|
||||
For Itanium
|
||||
#setpci -d 17d5:* 62=3d
|
||||
|
||||
For detailed description of the PCI registers, please see Xframe User Guide.
|
||||
|
||||
b. Ensure Transmit Checksum offload is enabled. Use ethtool to set/verify this
|
||||
parameter.
|
||||
c. Turn on TSO(using "ethtool -K")
|
||||
# ethtool -K <ethX> tso on
|
||||
|
||||
Receive performance:
|
||||
a. By default, the driver respects BIOS settings for PCI bus parameters.
|
||||
However, you may want to set PCI latency timer to 248.
|
||||
#setpci -d 17d5:* LATENCY_TIMER=f8
|
||||
For detailed description of the PCI registers, please see Xframe User Guide.
|
||||
b. Use 2-buffer mode. This results in large performance boost on
|
||||
on certain platforms(eg. SGI Altix, IBM xSeries).
|
||||
c. Ensure Receive Checksum offload is enabled. Use "ethtool -K ethX" command to
|
||||
set/verify this option.
|
||||
d. Enable NAPI feature(in kernel configuration Device Drivers ---> Network
|
||||
device support ---> Ethernet (10000 Mbit) ---> S2IO 10Gbe Xframe NIC) to
|
||||
bring down CPU utilization.
|
||||
|
||||
** For AMD opteron platforms with 8131 chipset, MMRBC=1 and MOST=1 are
|
||||
recommended as safe parameters.
|
||||
For more information, please review the AMD8131 errata at
|
||||
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26310.pdf
|
||||
|
||||
6. Available Downloads
|
||||
Neterion "s2io" driver in Red Hat and Suse 2.6-based distributions is kept up
|
||||
to date, also the latest "s2io" code (including support for 2.4 kernels) is
|
||||
available via "Support" link on the Neterion site: http://www.neterion.com.
|
||||
|
||||
For Xframe User Guide (Programming manual), visit ftp site ns1.s2io.com,
|
||||
user: linuxdocs password: HALdocs
|
||||
|
||||
7. Support
|
||||
For further support please contact either your 10GbE Xframe NIC vendor (IBM,
|
||||
HP, SGI etc.) or click on the "Support" link on the Neterion site:
|
||||
http://www.neterion.com.
|
||||
|
||||
|
|
|
|||
|
|
@ -910,6 +910,15 @@ L: linux-fbdev-devel@lists.sourceforge.net
|
|||
W: http://linux-fbdev.sourceforge.net/
|
||||
S: Maintained
|
||||
|
||||
FREESCALE SOC FS_ENET DRIVER
|
||||
P: Pantelis Antoniou
|
||||
M: pantelis.antoniou@gmail.com
|
||||
P: Vitaly Bordug
|
||||
M: vbordug@ru.mvista.com
|
||||
L: linuxppc-embedded@ozlabs.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
|
||||
FILE LOCKING (flock() and fcntl()/lockf())
|
||||
P: Matthew Wilcox
|
||||
M: matthew@wil.cx
|
||||
|
|
|
|||
|
|
@ -1203,7 +1203,7 @@ config IBM_EMAC_RX_SKB_HEADROOM
|
|||
|
||||
config IBM_EMAC_PHY_RX_CLK_FIX
|
||||
bool "PHY Rx clock workaround"
|
||||
depends on IBM_EMAC && (405EP || 440GX || 440EP)
|
||||
depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
|
||||
help
|
||||
Enable this if EMAC attached to a PHY which doesn't generate
|
||||
RX clock if there is no link, if this is the case, you will
|
||||
|
|
@ -2258,17 +2258,6 @@ config S2IO_NAPI
|
|||
|
||||
If in doubt, say N.
|
||||
|
||||
config 2BUFF_MODE
|
||||
bool "Use 2 Buffer Mode on Rx side."
|
||||
depends on S2IO
|
||||
---help---
|
||||
On enabling the 2 buffer mode, the received frame will be
|
||||
split into 2 parts before being DMA'ed to the hosts memory.
|
||||
The parts are the ethernet header and ethernet payload.
|
||||
This is useful on systems where DMA'ing to to unaligned
|
||||
physical memory loactions comes with a heavy price.
|
||||
If not sure please say N.
|
||||
|
||||
endmenu
|
||||
|
||||
if !UML
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
config FEC_8XX
|
||||
tristate "Motorola 8xx FEC driver"
|
||||
depends on NET_ETHERNET && 8xx && (NETTA || NETPHONE)
|
||||
depends on NET_ETHERNET
|
||||
select MII
|
||||
|
||||
config FEC_8XX_GENERIC_PHY
|
||||
|
|
@ -12,3 +12,9 @@ config FEC_8XX_DM9161_PHY
|
|||
bool "Support DM9161 PHY"
|
||||
depends on FEC_8XX
|
||||
default n
|
||||
|
||||
config FEC_8XX_LXT971_PHY
|
||||
bool "Support LXT971/LXT972 PHY"
|
||||
depends on FEC_8XX
|
||||
default n
|
||||
|
||||
|
|
|
|||
|
|
@ -203,6 +203,39 @@ static void dm9161_shutdown(struct net_device *dev)
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_8XX_LXT971_PHY
|
||||
|
||||
/* Support for LXT971/972 PHY */
|
||||
|
||||
#define MII_LXT971_PCR 16 /* Port Control Register */
|
||||
#define MII_LXT971_SR2 17 /* Status Register 2 */
|
||||
#define MII_LXT971_IER 18 /* Interrupt Enable Register */
|
||||
#define MII_LXT971_ISR 19 /* Interrupt Status Register */
|
||||
#define MII_LXT971_LCR 20 /* LED Control Register */
|
||||
#define MII_LXT971_TCR 30 /* Transmit Control Register */
|
||||
|
||||
static void lxt971_startup(struct net_device *dev)
|
||||
{
|
||||
struct fec_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x00F2);
|
||||
}
|
||||
|
||||
static void lxt971_ack_int(struct net_device *dev)
|
||||
{
|
||||
struct fec_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
fec_mii_read(dev, fep->mii_if.phy_id, MII_LXT971_ISR);
|
||||
}
|
||||
|
||||
static void lxt971_shutdown(struct net_device *dev)
|
||||
{
|
||||
struct fec_enet_private *fep = netdev_priv(dev);
|
||||
|
||||
fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x0000);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**********************************************************************************/
|
||||
|
||||
static const struct phy_info phy_info[] = {
|
||||
|
|
@ -215,6 +248,15 @@ static const struct phy_info phy_info[] = {
|
|||
.shutdown = dm9161_shutdown,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_FEC_8XX_LXT971_PHY
|
||||
{
|
||||
.id = 0x0001378e,
|
||||
.name = "LXT971/972",
|
||||
.startup = lxt971_startup,
|
||||
.ack_int = lxt971_ack_int,
|
||||
.shutdown = lxt971_shutdown,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_FEC_8XX_GENERIC_PHY
|
||||
{
|
||||
.id = 0,
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ static int fs_enet_rx_napi(struct net_device *dev, int *budget)
|
|||
|
||||
skb = fep->rx_skbuff[curidx];
|
||||
|
||||
dma_unmap_single(fep->dev, skb->data,
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
|
@ -144,7 +144,7 @@ static int fs_enet_rx_napi(struct net_device *dev, int *budget)
|
|||
|
||||
skb = fep->rx_skbuff[curidx];
|
||||
|
||||
dma_unmap_single(fep->dev, skb->data,
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
|
@ -268,7 +268,7 @@ static int fs_enet_rx_non_napi(struct net_device *dev)
|
|||
|
||||
skb = fep->rx_skbuff[curidx];
|
||||
|
||||
dma_unmap_single(fep->dev, skb->data,
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
|
@ -278,7 +278,7 @@ static int fs_enet_rx_non_napi(struct net_device *dev)
|
|||
|
||||
skb = fep->rx_skbuff[curidx];
|
||||
|
||||
dma_unmap_single(fep->dev, skb->data,
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
|
@ -399,7 +399,8 @@ static void fs_enet_tx(struct net_device *dev)
|
|||
fep->stats.collisions++;
|
||||
|
||||
/* unmap */
|
||||
dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
skb->len, DMA_TO_DEVICE);
|
||||
|
||||
/*
|
||||
* Free the sk buffer associated with this last transmit.
|
||||
|
|
@ -547,17 +548,19 @@ void fs_cleanup_bds(struct net_device *dev)
|
|||
{
|
||||
struct fs_enet_private *fep = netdev_priv(dev);
|
||||
struct sk_buff *skb;
|
||||
cbd_t *bdp;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Reset SKB transmit buffers.
|
||||
*/
|
||||
for (i = 0; i < fep->tx_ring; i++) {
|
||||
for (i = 0, bdp = fep->tx_bd_base; i < fep->tx_ring; i++, bdp++) {
|
||||
if ((skb = fep->tx_skbuff[i]) == NULL)
|
||||
continue;
|
||||
|
||||
/* unmap */
|
||||
dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
skb->len, DMA_TO_DEVICE);
|
||||
|
||||
fep->tx_skbuff[i] = NULL;
|
||||
dev_kfree_skb(skb);
|
||||
|
|
@ -566,12 +569,12 @@ void fs_cleanup_bds(struct net_device *dev)
|
|||
/*
|
||||
* Reset SKB receive buffers
|
||||
*/
|
||||
for (i = 0; i < fep->rx_ring; i++) {
|
||||
for (i = 0, bdp = fep->rx_bd_base; i < fep->rx_ring; i++, bdp++) {
|
||||
if ((skb = fep->rx_skbuff[i]) == NULL)
|
||||
continue;
|
||||
|
||||
/* unmap */
|
||||
dma_unmap_single(fep->dev, skb->data,
|
||||
dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
|
||||
L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@
|
|||
/* This is a simple check to prevent use of this driver on non-tested SoCs */
|
||||
#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
|
||||
!defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
|
||||
!defined(CONFIG_440EP) && !defined(CONFIG_NP405H)
|
||||
!defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
|
||||
!defined(CONFIG_440GR)
|
||||
#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
|
||||
#endif
|
||||
|
||||
|
|
@ -246,6 +247,25 @@ struct emac_regs {
|
|||
#define EMAC_STACR_PCDA_SHIFT 5
|
||||
#define EMAC_STACR_PRA_MASK 0x1f
|
||||
|
||||
/*
|
||||
* For the 440SPe, AMCC inexplicably changed the polarity of
|
||||
* the "operation complete" bit in the MII control register.
|
||||
*/
|
||||
#if defined(CONFIG_440SPE)
|
||||
static inline int emac_phy_done(u32 stacr)
|
||||
{
|
||||
return !(stacr & EMAC_STACR_OC);
|
||||
};
|
||||
#define EMAC_STACR_START EMAC_STACR_OC
|
||||
|
||||
#else /* CONFIG_440SPE */
|
||||
static inline int emac_phy_done(u32 stacr)
|
||||
{
|
||||
return stacr & EMAC_STACR_OC;
|
||||
};
|
||||
#define EMAC_STACR_START 0
|
||||
#endif /* !CONFIG_440SPE */
|
||||
|
||||
/* EMACx_TRTR */
|
||||
#if !defined(CONFIG_IBM_EMAC4)
|
||||
#define EMAC_TRTR_SHIFT 27
|
||||
|
|
|
|||
|
|
@ -87,10 +87,11 @@ MODULE_LICENSE("GPL");
|
|||
*/
|
||||
static u32 busy_phy_map;
|
||||
|
||||
#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP))
|
||||
#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
|
||||
(defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
|
||||
/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
|
||||
* with PHY RX clock problem.
|
||||
* 440EP has more sane SDR0_MFR register implementation than 440GX, which
|
||||
* 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
|
||||
* also allows controlling each EMAC clock
|
||||
*/
|
||||
static inline void EMAC_RX_CLK_TX(int idx)
|
||||
|
|
@ -100,7 +101,7 @@ static inline void EMAC_RX_CLK_TX(int idx)
|
|||
|
||||
#if defined(CONFIG_405EP)
|
||||
mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
|
||||
#else /* CONFIG_440EP */
|
||||
#else /* CONFIG_440EP || CONFIG_440GR */
|
||||
SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
|
||||
#endif
|
||||
|
||||
|
|
@ -546,7 +547,7 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
|
|||
|
||||
/* Wait for management interface to become idle */
|
||||
n = 10;
|
||||
while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
|
||||
while (!emac_phy_done(in_be32(&p->stacr))) {
|
||||
udelay(1);
|
||||
if (!--n)
|
||||
goto to;
|
||||
|
|
@ -556,11 +557,12 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
|
|||
out_be32(&p->stacr,
|
||||
EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
|
||||
(reg & EMAC_STACR_PRA_MASK)
|
||||
| ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT));
|
||||
| ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
|
||||
| EMAC_STACR_START);
|
||||
|
||||
/* Wait for read to complete */
|
||||
n = 100;
|
||||
while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) {
|
||||
while (!emac_phy_done(r = in_be32(&p->stacr))) {
|
||||
udelay(1);
|
||||
if (!--n)
|
||||
goto to;
|
||||
|
|
@ -594,7 +596,7 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
|
|||
|
||||
/* Wait for management interface to be idle */
|
||||
n = 10;
|
||||
while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
|
||||
while (!emac_phy_done(in_be32(&p->stacr))) {
|
||||
udelay(1);
|
||||
if (!--n)
|
||||
goto to;
|
||||
|
|
@ -605,11 +607,11 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
|
|||
EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
|
||||
(reg & EMAC_STACR_PRA_MASK) |
|
||||
((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
|
||||
(val << EMAC_STACR_PHYD_SHIFT));
|
||||
(val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
|
||||
|
||||
/* Wait for write to complete */
|
||||
n = 100;
|
||||
while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
|
||||
while (!emac_phy_done(in_be32(&p->stacr))) {
|
||||
udelay(1);
|
||||
if (!--n)
|
||||
goto to;
|
||||
|
|
|
|||
|
|
@ -32,9 +32,10 @@
|
|||
* reflect the fact that 40x and 44x have slightly different MALs. --ebs
|
||||
*/
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_NP405H)
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
|
||||
#define MAL_VERSION 1
|
||||
#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
|
||||
defined(CONFIG_440SPE)
|
||||
#define MAL_VERSION 2
|
||||
#else
|
||||
#error "Unknown SoC, please check chip manual and choose MAL 'version'"
|
||||
|
|
|
|||
|
|
@ -236,12 +236,16 @@ static struct mii_phy_def genmii_phy_def = {
|
|||
};
|
||||
|
||||
/* CIS8201 */
|
||||
#define MII_CIS8201_10BTCSR 0x16
|
||||
#define TENBTCSR_ECHO_DISABLE 0x2000
|
||||
#define MII_CIS8201_EPCR 0x17
|
||||
#define EPCR_MODE_MASK 0x3000
|
||||
#define EPCR_GMII_MODE 0x0000
|
||||
#define EPCR_RGMII_MODE 0x1000
|
||||
#define EPCR_TBI_MODE 0x2000
|
||||
#define EPCR_RTBI_MODE 0x3000
|
||||
#define MII_CIS8201_ACSR 0x1c
|
||||
#define ACSR_PIN_PRIO_SELECT 0x0004
|
||||
|
||||
static int cis8201_init(struct mii_phy *phy)
|
||||
{
|
||||
|
|
@ -269,6 +273,14 @@ static int cis8201_init(struct mii_phy *phy)
|
|||
}
|
||||
|
||||
phy_write(phy, MII_CIS8201_EPCR, epcr);
|
||||
|
||||
/* MII regs override strap pins */
|
||||
phy_write(phy, MII_CIS8201_ACSR,
|
||||
phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
|
||||
|
||||
/* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
|
||||
phy_write(phy, MII_CIS8201_10BTCSR,
|
||||
phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,8 +22,8 @@
|
|||
*************************************************************************/
|
||||
|
||||
#define DRV_NAME "pcnet32"
|
||||
#define DRV_VERSION "1.31a"
|
||||
#define DRV_RELDATE "12.Sep.2005"
|
||||
#define DRV_VERSION "1.31c"
|
||||
#define DRV_RELDATE "01.Nov.2005"
|
||||
#define PFX DRV_NAME ": "
|
||||
|
||||
static const char *version =
|
||||
|
|
@ -260,6 +260,11 @@ static int homepna[MAX_UNITS];
|
|||
* v1.31 02 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> added set_ringparam().
|
||||
* v1.31a 12 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> set min ring size to 4
|
||||
* to allow loopback test to work unchanged.
|
||||
* v1.31b 06 Oct 2005 Don Fry changed alloc_ring to show name of device
|
||||
* if allocation fails
|
||||
* v1.31c 01 Nov 2005 Don Fry Allied Telesyn 2700/2701 FX are 100Mbit only.
|
||||
* Force 100Mbit FD if Auto (ASEL) is selected.
|
||||
* See Bugzilla 2669 and 4551.
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -408,7 +413,7 @@ static int pcnet32_get_regs_len(struct net_device *dev);
|
|||
static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
||||
void *ptr);
|
||||
static void pcnet32_purge_tx_ring(struct net_device *dev);
|
||||
static int pcnet32_alloc_ring(struct net_device *dev);
|
||||
static int pcnet32_alloc_ring(struct net_device *dev, char *name);
|
||||
static void pcnet32_free_ring(struct net_device *dev);
|
||||
|
||||
|
||||
|
|
@ -669,15 +674,17 @@ static int pcnet32_set_ringparam(struct net_device *dev, struct ethtool_ringpara
|
|||
lp->rx_mod_mask = lp->rx_ring_size - 1;
|
||||
lp->rx_len_bits = (i << 4);
|
||||
|
||||
if (pcnet32_alloc_ring(dev)) {
|
||||
if (pcnet32_alloc_ring(dev, dev->name)) {
|
||||
pcnet32_free_ring(dev);
|
||||
spin_unlock_irqrestore(&lp->lock, flags);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&lp->lock, flags);
|
||||
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_INFO PFX "Ring Param Settings: RX: %d, TX: %d\n", lp->rx_ring_size, lp->tx_ring_size);
|
||||
printk(KERN_INFO PFX "%s: Ring Param Settings: RX: %d, TX: %d\n",
|
||||
dev->name, lp->rx_ring_size, lp->tx_ring_size);
|
||||
|
||||
if (netif_running(dev))
|
||||
pcnet32_open(dev);
|
||||
|
|
@ -981,7 +988,11 @@ static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
|||
*buff++ = a->read_csr(ioaddr, 114);
|
||||
|
||||
/* read bus configuration registers */
|
||||
for (i=0; i<36; i++) {
|
||||
for (i=0; i<30; i++) {
|
||||
*buff++ = a->read_bcr(ioaddr, i);
|
||||
}
|
||||
*buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
|
||||
for (i=31; i<36; i++) {
|
||||
*buff++ = a->read_bcr(ioaddr, i);
|
||||
}
|
||||
|
||||
|
|
@ -1340,7 +1351,8 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
|||
}
|
||||
lp->a = *a;
|
||||
|
||||
if (pcnet32_alloc_ring(dev)) {
|
||||
/* prior to register_netdev, dev->name is not yet correct */
|
||||
if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_ring;
|
||||
}
|
||||
|
|
@ -1448,48 +1460,63 @@ err_release_region:
|
|||
}
|
||||
|
||||
|
||||
static int pcnet32_alloc_ring(struct net_device *dev)
|
||||
/* if any allocation fails, caller must also call pcnet32_free_ring */
|
||||
static int pcnet32_alloc_ring(struct net_device *dev, char *name)
|
||||
{
|
||||
struct pcnet32_private *lp = dev->priv;
|
||||
|
||||
if ((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
|
||||
&lp->tx_ring_dma_addr)) == NULL) {
|
||||
lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
|
||||
sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
|
||||
&lp->tx_ring_dma_addr);
|
||||
if (lp->tx_ring == NULL) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n",
|
||||
name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if ((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
|
||||
&lp->rx_ring_dma_addr)) == NULL) {
|
||||
lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
|
||||
sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
|
||||
&lp->rx_ring_dma_addr);
|
||||
if (lp->rx_ring == NULL) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n",
|
||||
name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (!(lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, GFP_ATOMIC))) {
|
||||
lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size,
|
||||
GFP_ATOMIC);
|
||||
if (!lp->tx_dma_addr) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size);
|
||||
|
||||
if (!(lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, GFP_ATOMIC))) {
|
||||
lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size,
|
||||
GFP_ATOMIC);
|
||||
if (!lp->rx_dma_addr) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size);
|
||||
|
||||
if (!(lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, GFP_ATOMIC))) {
|
||||
lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size,
|
||||
GFP_ATOMIC);
|
||||
if (!lp->tx_skbuff) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size);
|
||||
|
||||
if (!(lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, GFP_ATOMIC))) {
|
||||
lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size,
|
||||
GFP_ATOMIC);
|
||||
if (!lp->rx_skbuff) {
|
||||
if (pcnet32_debug & NETIF_MSG_DRV)
|
||||
printk(KERN_ERR PFX "Memory allocation failed.\n");
|
||||
printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size);
|
||||
|
|
@ -1592,12 +1619,18 @@ pcnet32_open(struct net_device *dev)
|
|||
val |= 0x10;
|
||||
lp->a.write_csr (ioaddr, 124, val);
|
||||
|
||||
/* Allied Telesyn AT 2700/2701 FX looses the link, so skip that */
|
||||
/* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
|
||||
if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
|
||||
(lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
|
||||
lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
|
||||
printk(KERN_DEBUG "%s: Skipping PHY selection.\n", dev->name);
|
||||
} else {
|
||||
(lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
|
||||
lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
|
||||
if (lp->options & PCNET32_PORT_ASEL) {
|
||||
lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
|
||||
if (netif_msg_link(lp))
|
||||
printk(KERN_DEBUG "%s: Setting 100Mb-Full Duplex.\n",
|
||||
dev->name);
|
||||
}
|
||||
}
|
||||
{
|
||||
/*
|
||||
* 24 Jun 2004 according AMD, in order to change the PHY,
|
||||
* DANAS (or DISPM for 79C976) must be set; then select the speed,
|
||||
|
|
|
|||
|
|
@ -61,6 +61,9 @@ int mdiobus_register(struct mii_bus *bus)
|
|||
for (i = 0; i < PHY_MAX_ADDR; i++) {
|
||||
struct phy_device *phydev;
|
||||
|
||||
if (bus->phy_mask & (1 << i))
|
||||
continue;
|
||||
|
||||
phydev = get_phy_device(bus, i);
|
||||
|
||||
if (IS_ERR(phydev))
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -418,7 +418,7 @@ typedef struct list_info_hold {
|
|||
void *list_virt_addr;
|
||||
} list_info_hold_t;
|
||||
|
||||
/* Rx descriptor structure */
|
||||
/* Rx descriptor structure for 1 buffer mode */
|
||||
typedef struct _RxD_t {
|
||||
u64 Host_Control; /* reserved for host */
|
||||
u64 Control_1;
|
||||
|
|
@ -439,49 +439,54 @@ typedef struct _RxD_t {
|
|||
#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
|
||||
#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
|
||||
|
||||
#ifndef CONFIG_2BUFF_MODE
|
||||
#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
|
||||
#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
|
||||
#else
|
||||
#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
|
||||
#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
|
||||
#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
|
||||
#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
|
||||
#define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
|
||||
#define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
|
||||
#endif
|
||||
|
||||
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
|
||||
#define SET_VLAN_TAG(val) vBIT(val,48,16)
|
||||
#define SET_NUM_TAG(val) vBIT(val,16,32)
|
||||
|
||||
#ifndef CONFIG_2BUFF_MODE
|
||||
#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
|
||||
#else
|
||||
#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
|
||||
>> 48)
|
||||
#define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
|
||||
>> 32)
|
||||
#define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
|
||||
>> 16)
|
||||
|
||||
} RxD_t;
|
||||
/* Rx descriptor structure for 1 buffer mode */
|
||||
typedef struct _RxD1_t {
|
||||
struct _RxD_t h;
|
||||
|
||||
#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
|
||||
#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
|
||||
#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
|
||||
(u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
|
||||
u64 Buffer0_ptr;
|
||||
} RxD1_t;
|
||||
/* Rx descriptor structure for 3 or 2 buffer mode */
|
||||
|
||||
typedef struct _RxD3_t {
|
||||
struct _RxD_t h;
|
||||
|
||||
#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
|
||||
#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
|
||||
#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
|
||||
#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
|
||||
#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
|
||||
#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
|
||||
#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
|
||||
(u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
|
||||
#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
|
||||
(u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
|
||||
#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
|
||||
(u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
|
||||
#define BUF0_LEN 40
|
||||
#define BUF1_LEN 1
|
||||
#endif
|
||||
|
||||
u64 Buffer0_ptr;
|
||||
#ifdef CONFIG_2BUFF_MODE
|
||||
u64 Buffer1_ptr;
|
||||
u64 Buffer2_ptr;
|
||||
#endif
|
||||
} RxD_t;
|
||||
} RxD3_t;
|
||||
|
||||
|
||||
/* Structure that represents the Rx descriptor block which contains
|
||||
* 128 Rx descriptors.
|
||||
*/
|
||||
#ifndef CONFIG_2BUFF_MODE
|
||||
typedef struct _RxD_block {
|
||||
#define MAX_RXDS_PER_BLOCK 127
|
||||
RxD_t rxd[MAX_RXDS_PER_BLOCK];
|
||||
#define MAX_RXDS_PER_BLOCK_1 127
|
||||
RxD1_t rxd[MAX_RXDS_PER_BLOCK_1];
|
||||
|
||||
u64 reserved_0;
|
||||
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
|
||||
|
|
@ -492,18 +497,13 @@ typedef struct _RxD_block {
|
|||
* the upper 32 bits should
|
||||
* be 0 */
|
||||
} RxD_block_t;
|
||||
#else
|
||||
typedef struct _RxD_block {
|
||||
#define MAX_RXDS_PER_BLOCK 85
|
||||
RxD_t rxd[MAX_RXDS_PER_BLOCK];
|
||||
|
||||
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
|
||||
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
|
||||
* in this blk */
|
||||
u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
|
||||
} RxD_block_t;
|
||||
#define SIZE_OF_BLOCK 4096
|
||||
|
||||
#define RXD_MODE_1 0
|
||||
#define RXD_MODE_3A 1
|
||||
#define RXD_MODE_3B 2
|
||||
|
||||
/* Structure to hold virtual addresses of Buf0 and Buf1 in
|
||||
* 2buf mode. */
|
||||
typedef struct bufAdd {
|
||||
|
|
@ -512,7 +512,6 @@ typedef struct bufAdd {
|
|||
void *ba_0;
|
||||
void *ba_1;
|
||||
} buffAdd_t;
|
||||
#endif
|
||||
|
||||
/* Structure which stores all the MAC control parameters */
|
||||
|
||||
|
|
@ -539,10 +538,17 @@ typedef struct {
|
|||
|
||||
typedef tx_curr_get_info_t tx_curr_put_info_t;
|
||||
|
||||
|
||||
typedef struct rxd_info {
|
||||
void *virt_addr;
|
||||
dma_addr_t dma_addr;
|
||||
}rxd_info_t;
|
||||
|
||||
/* Structure that holds the Phy and virt addresses of the Blocks */
|
||||
typedef struct rx_block_info {
|
||||
RxD_t *block_virt_addr;
|
||||
void *block_virt_addr;
|
||||
dma_addr_t block_dma_addr;
|
||||
rxd_info_t *rxds;
|
||||
} rx_block_info_t;
|
||||
|
||||
/* pre declaration of the nic structure */
|
||||
|
|
@ -578,10 +584,8 @@ typedef struct ring_info {
|
|||
int put_pos;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_2BUFF_MODE
|
||||
/* Buffer Address store. */
|
||||
buffAdd_t **ba;
|
||||
#endif
|
||||
nic_t *nic;
|
||||
} ring_info_t;
|
||||
|
||||
|
|
@ -647,8 +651,6 @@ typedef struct {
|
|||
|
||||
/* Default Tunable parameters of the NIC. */
|
||||
#define DEFAULT_FIFO_LEN 4096
|
||||
#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
|
||||
#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
|
||||
#define SMALL_BLK_CNT 30
|
||||
#define LARGE_BLK_CNT 100
|
||||
|
||||
|
|
@ -678,6 +680,7 @@ struct msix_info_st {
|
|||
|
||||
/* Structure representing one instance of the NIC */
|
||||
struct s2io_nic {
|
||||
int rxd_mode;
|
||||
#ifdef CONFIG_S2IO_NAPI
|
||||
/*
|
||||
* Count of packets to be processed in a given iteration, it will be indicated
|
||||
|
|
|
|||
|
|
@ -2040,7 +2040,7 @@ static int mpi_send_packet (struct net_device *dev)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void get_tx_error(struct airo_info *ai, u32 fid)
|
||||
static void get_tx_error(struct airo_info *ai, s32 fid)
|
||||
{
|
||||
u16 status;
|
||||
|
||||
|
|
|
|||
|
|
@ -72,6 +72,9 @@ struct mii_bus {
|
|||
/* list of all PHYs on bus */
|
||||
struct phy_device *phy_map[PHY_MAX_ADDR];
|
||||
|
||||
/* Phy addresses to be ignored when probing */
|
||||
u32 phy_mask;
|
||||
|
||||
/* Pointer to an array of interrupts, each PHY's
|
||||
* interrupt at the index matching its address */
|
||||
int *irq;
|
||||
|
|
|
|||
Loading…
Reference in New Issue