arm64: errata: Add detection for TRBE trace data corruption
TRBE implementations affected by Arm erratum #1902691 might corrupt trace data or deadlock, when it's being written into the memory. So effectively TRBE is broken and hence cannot be used to capture trace data. This adds a new errata ARM64_ERRATUM_1902691 in arm64 errata framework. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki Poulose <suzuki.poulose@arm.com> Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1643120437-14352-5-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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@ -56,6 +56,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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@ -819,6 +819,24 @@ config ARM64_ERRATUM_2038923
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If unsure, say Y.
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config ARM64_ERRATUM_1902691
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bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 1902691.
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Affected Cortex-A510 core might cause trace data corruption, when being written
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into the memory. Effectively TRBE is broken and hence cannot be used to capture
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trace data.
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Work around this problem in the driver by just preventing TRBE initialization on
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affected cpus. The firmware must have disabled the access to TRBE for the kernel
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on such implementations. This will cover the kernel for any firmware that doesn't
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do this already.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y
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@ -615,6 +615,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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/* Cortex-A510 r0p0 - r0p2 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1902691
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{
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.desc = "ARM erratum 1902691",
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.capability = ARM64_WORKAROUND_1902691,
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/* Cortex-A510 r0p0 - r0p1 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
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},
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#endif
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{
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}
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@ -57,6 +57,7 @@ WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_2064142
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WORKAROUND_2038923
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WORKAROUND_1902691
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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