drm/amd/display: Store tiling_flags and tmz_surface on dm_plane_state
[Why] Store these in advance so we can reuse them later in commit_tail without having to reserve the fbo again. These will also be used for checking for tiling changes when deciding to reset the plane or not. [How] This change should mostly be a refactor. Only commit check is affected for now and I'll drop the get_fb_info calls in prepare_planes and commit_tail after. This runs a prepass loop once we think that all planes have been added to the context and replaces the get_fb_info calls with accessing the dm_plane_state instead. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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707477b086
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@ -3627,8 +3627,17 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state,
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static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
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uint64_t *tiling_flags, bool *tmz_surface)
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{
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struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
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int r = amdgpu_bo_reserve(rbo, false);
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struct amdgpu_bo *rbo;
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int r;
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if (!amdgpu_fb) {
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*tiling_flags = 0;
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*tmz_surface = false;
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return 0;
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}
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rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
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r = amdgpu_bo_reserve(rbo, false);
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if (unlikely(r)) {
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/* Don't show error message when returning -ERESTARTSYS */
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@ -4051,13 +4060,10 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
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struct drm_crtc_state *crtc_state)
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{
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struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
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const struct amdgpu_framebuffer *amdgpu_fb =
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to_amdgpu_framebuffer(plane_state->fb);
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struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
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struct dc_scaling_info scaling_info;
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struct dc_plane_info plane_info;
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uint64_t tiling_flags;
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int ret;
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bool tmz_surface = false;
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bool force_disable_dcc = false;
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ret = fill_dc_scaling_info(plane_state, &scaling_info);
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@ -4069,15 +4075,12 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
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dc_plane_state->clip_rect = scaling_info.clip_rect;
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dc_plane_state->scaling_quality = scaling_info.scaling_quality;
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ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
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if (ret)
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return ret;
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force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
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ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
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ret = fill_dc_plane_info_and_addr(adev, plane_state,
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dm_plane_state->tiling_flags,
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&plane_info,
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&dc_plane_state->address,
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tmz_surface,
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dm_plane_state->tmz_surface,
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force_disable_dcc);
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if (ret)
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return ret;
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@ -5675,6 +5678,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
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dc_plane_state_retain(dm_plane_state->dc_state);
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}
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/* Framebuffer hasn't been updated yet, so retain old flags. */
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dm_plane_state->tiling_flags = old_dm_plane_state->tiling_flags;
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dm_plane_state->tmz_surface = old_dm_plane_state->tmz_surface;
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return &dm_plane_state->base;
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}
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@ -8482,13 +8489,9 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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continue;
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
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const struct amdgpu_framebuffer *amdgpu_fb =
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to_amdgpu_framebuffer(new_plane_state->fb);
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struct dc_plane_info *plane_info = &bundle->plane_infos[num_plane];
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struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane];
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struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane];
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uint64_t tiling_flags;
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bool tmz_surface = false;
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new_plane_crtc = new_plane_state->crtc;
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new_dm_plane_state = to_dm_plane_state(new_plane_state);
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@ -8535,16 +8538,12 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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bundle->surface_updates[num_plane].scaling_info = scaling_info;
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if (amdgpu_fb) {
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ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
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if (ret)
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goto cleanup;
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if (new_plane_state->fb) {
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ret = fill_dc_plane_info_and_addr(
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dm->adev, new_plane_state, tiling_flags,
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plane_info,
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&flip_addr->address, tmz_surface,
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false);
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dm->adev, new_plane_state,
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new_dm_plane_state->tiling_flags,
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plane_info, &flip_addr->address,
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new_dm_plane_state->tmz_surface, false);
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if (ret)
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goto cleanup;
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@ -8758,6 +8757,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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}
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}
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/* Prepass for updating tiling flags on new planes. */
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for_each_new_plane_in_state(state, plane, new_plane_state, i) {
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struct dm_plane_state *new_dm_plane_state = to_dm_plane_state(new_plane_state);
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struct amdgpu_framebuffer *new_afb = to_amdgpu_framebuffer(new_plane_state->fb);
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ret = get_fb_info(new_afb, &new_dm_plane_state->tiling_flags,
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&new_dm_plane_state->tmz_surface);
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if (ret)
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goto fail;
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}
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/* Remove exiting planes if they are modified */
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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ret = dm_update_plane_state(dc, state, plane,
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@ -412,6 +412,8 @@ struct dc_plane_state;
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struct dm_plane_state {
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struct drm_plane_state base;
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struct dc_plane_state *dc_state;
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uint64_t tiling_flags;
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bool tmz_surface;
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};
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struct dm_crtc_state {
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