ASoC: fsl_ssi: Set xFEN0 and xFEN1 together
It'd be safer to enable both FIFOs for TX or RX at the same time. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Tested-by: Caleb Crome <caleb@crome.org> Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Reviewed-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -591,6 +591,11 @@ static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
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if (fsl_ssi_is_ac97(ssi))
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if (fsl_ssi_is_ac97(ssi))
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vals[RX].scr = vals[TX].scr = 0;
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vals[RX].scr = vals[TX].scr = 0;
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if (ssi->use_dual_fifo) {
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vals[RX].srcr |= SSI_SRCR_RFEN1;
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vals[TX].stcr |= SSI_STCR_TFEN1;
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}
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if (ssi->use_dma) {
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if (ssi->use_dma) {
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vals[RX].sier |= SSI_SIER_RDMAE;
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vals[RX].sier |= SSI_SIER_RDMAE;
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vals[TX].sier |= SSI_SIER_TDMAE;
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vals[TX].sier |= SSI_SIER_TDMAE;
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@ -991,14 +996,9 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
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SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
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SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
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SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
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SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
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if (ssi->use_dual_fifo) {
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if (ssi->use_dual_fifo)
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regmap_update_bits(regs, REG_SSI_SRCR,
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SSI_SRCR_RFEN1, SSI_SRCR_RFEN1);
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regmap_update_bits(regs, REG_SSI_STCR,
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SSI_STCR_TFEN1, SSI_STCR_TFEN1);
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regmap_update_bits(regs, REG_SSI_SCR,
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regmap_update_bits(regs, REG_SSI_SCR,
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SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
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SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
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}
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if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
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if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
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fsl_ssi_setup_ac97(ssi);
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fsl_ssi_setup_ac97(ssi);
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