[PARISC] spelling fixes: arch/parisc/
Spelling fixes in arch/parisc/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Acked-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Simon Arlott
Kyle McMartin
parent
b5e8b733a1
commit
7022672e40
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@ -634,7 +634,7 @@ EXPORT_SYMBOL(pdc_lan_station_id);
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* pdc_stable_read - Read data from Stable Storage.
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* @staddr: Stable Storage address to access.
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* @memaddr: The memory address where Stable Storage data shall be copied.
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* @count: number of bytes to transfert. count is multiple of 4.
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* @count: number of bytes to transfer. count is multiple of 4.
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*
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* This PDC call reads from the Stable Storage address supplied in staddr
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* and copies count bytes to the memory address memaddr.
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@ -660,7 +660,7 @@ EXPORT_SYMBOL(pdc_stable_read);
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* pdc_stable_write - Write data to Stable Storage.
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* @staddr: Stable Storage address to access.
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* @memaddr: The memory address where Stable Storage data shall be read from.
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* @count: number of bytes to transfert. count is multiple of 4.
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* @count: number of bytes to transfer. count is multiple of 4.
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*
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* This PDC call reads count bytes from the supplied memaddr address,
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* and copies count bytes to the Stable Storage address staddr.
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@ -576,27 +576,27 @@ static int perf_stop_counters(uint32_t *raddr)
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if (!perf_rdr_read_ubuf(16, userbuf))
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return -13;
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/* Counter0 is bits 1398 thru 1429 */
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/* Counter0 is bits 1398 to 1429 */
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tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
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tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
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/* OR sticky0 (bit 1430) to counter0 bit 32 */
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tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
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raddr[0] = (uint32_t)tmp64;
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/* Counter1 is bits 1431 thru 1462 */
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/* Counter1 is bits 1431 to 1462 */
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tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
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/* OR sticky1 (bit 1463) to counter1 bit 32 */
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tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
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raddr[1] = (uint32_t)tmp64;
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/* Counter2 is bits 1464 thru 1495 */
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/* Counter2 is bits 1464 to 1495 */
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tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
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tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
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/* OR sticky2 (bit 1496) to counter2 bit 32 */
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tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
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raddr[2] = (uint32_t)tmp64;
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/* Counter3 is bits 1497 thru 1528 */
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/* Counter3 is bits 1497 to 1528 */
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tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
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/* OR sticky3 (bit 1529) to counter3 bit 32 */
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tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
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@ -618,7 +618,7 @@ static int perf_stop_counters(uint32_t *raddr)
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userbuf[23] = 0;
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/*
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* Write back the zero'ed bytes + the image given
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* Write back the zeroed bytes + the image given
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* the read was destructive.
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*/
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perf_rdr_write(16, userbuf);
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@ -63,7 +63,7 @@ extern int update_cr16_clocksource(void); /* from time.c */
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** will call register_parisc_driver(&cpu_driver) before calling do_inventory().
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**
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** The goal of consolidating CPU initialization into one place is
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** to make sure all CPU's get initialized the same way.
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** to make sure all CPUs get initialized the same way.
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** The code path not shared is how PDC hands control of the CPU to the OS.
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** The initialization of OS data structures is the same (done below).
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*/
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@ -166,7 +166,7 @@ static int __init processor_probe(struct parisc_device *dev)
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#endif
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/*
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** CONFIG_SMP: init_smp_config() will attempt to get CPU's into
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** CONFIG_SMP: init_smp_config() will attempt to get CPUs into
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** OS control. RENDEZVOUS is the default state - see mem_set above.
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** p->state = STATE_RENDEZVOUS;
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*/
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@ -334,7 +334,7 @@ int __init init_per_cpu(int cpunum)
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}
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/*
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* Display cpu info for all cpu's.
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* Display CPU info for all CPUs.
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*/
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int
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show_cpuinfo (struct seq_file *m, void *v)
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@ -393,7 +393,7 @@ static struct parisc_driver cpu_driver __read_mostly = {
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};
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/**
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* processor_init - Processor initalization procedure.
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* processor_init - Processor initialization procedure.
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*
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* Register this driver.
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*/
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@ -162,7 +162,7 @@ void __init setup_arch(char **cmdline_p)
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}
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/*
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* Display cpu info for all cpu's.
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* Display CPU info for all CPUs.
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* for parisc this is in processor.c
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*/
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extern int show_cpuinfo (struct seq_file *m, void *v);
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@ -419,7 +419,7 @@ smp_cpu_init(int cpunum)
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BUG();
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enter_lazy_tlb(&init_mm, current);
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init_IRQ(); /* make sure no IRQ's are enabled or pending */
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init_IRQ(); /* make sure no IRQs are enabled or pending */
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start_cpu_itimer();
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}
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@ -552,7 +552,7 @@ void __devinit smp_prepare_boot_cpu(void)
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/*
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** inventory.c:do_inventory() hasn't yet been run and thus we
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** don't 'discover' the additional CPU's until later.
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** don't 'discover' the additional CPUs until later.
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*/
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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@ -191,7 +191,7 @@ int update_cr16_clocksource(void)
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{
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int change = 0;
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/* since the cr16 cycle counters are not syncronized across CPUs,
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/* since the cr16 cycle counters are not synchronized across CPUs,
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we'll check if we should switch to a safe clocksource: */
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if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) {
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clocksource_change_rating(&clocksource_cr16, 0);
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@ -615,7 +615,7 @@ void handle_interruption(int code, struct pt_regs *regs)
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case 13:
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/* Conditional Trap
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The condition succees in an instruction which traps
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The condition succeeds in an instruction which traps
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on condition */
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if(user_mode(regs)){
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si.si_signo = SIGFPE;
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@ -22,7 +22,7 @@
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PA header file -- do not include this header file for non-PA builds.
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#endif
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/* 32-bit word grabing functions */
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/* 32-bit word grabbing functions */
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#define Dbl_firstword(value) Dallp1(value)
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#define Dbl_secondword(value) Dallp2(value)
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#define Dbl_thirdword(value) dummy_location
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@ -37,7 +37,7 @@
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#define Dbl_allp1(object) Dallp1(object)
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#define Dbl_allp2(object) Dallp2(object)
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/* dbl_and_signs ands the sign bits of each argument and puts the result
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/* dbl_and_signs ANDs the sign bits of each argument and puts the result
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* into the first argument. dbl_or_signs ors those same sign bits */
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#define Dbl_and_signs( src1dst, src2) \
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Dallp1(src1dst) = (Dallp1(src2)|~((unsigned int)1<<31)) & Dallp1(src1dst)
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@ -76,7 +76,7 @@ dbl_fsqrt(
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}
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/*
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* Return quiet NaN or positive infinity.
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* Fall thru to negative test if negative infinity.
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* Fall through to negative test if negative infinity.
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*/
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if (Dbl_iszero_sign(srcp1) ||
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Dbl_isnotzero_mantissa(srcp1,srcp2)) {
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@ -76,7 +76,7 @@ sgl_fsqrt(
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}
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/*
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* Return quiet NaN or positive infinity.
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* Fall thru to negative test if negative infinity.
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* Fall through to negative test if negative infinity.
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*/
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if (Sgl_iszero_sign(src) || Sgl_isnotzero_mantissa(src)) {
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*dstptr = src;
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@ -23,7 +23,7 @@
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PA header file -- do not include this header file for non-PA builds.
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#endif
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/* 32-bit word grabing functions */
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/* 32-bit word grabbing functions */
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#define Sgl_firstword(value) Sall(value)
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#define Sgl_secondword(value) dummy_location
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#define Sgl_thirdword(value) dummy_location
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@ -36,7 +36,7 @@
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#define Sgl_exponentmantissa(object) Sexponentmantissa(object)
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#define Sgl_all(object) Sall(object)
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/* sgl_and_signs ands the sign bits of each argument and puts the result
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/* sgl_and_signs ANDs the sign bits of each argument and puts the result
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* into the first argument. sgl_or_signs ors those same sign bits */
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#define Sgl_and_signs( src1dst, src2) \
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Sall(src1dst) = (Sall(src2)|~((unsigned int)1<<31)) & Sall(src1dst)
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@ -890,7 +890,7 @@ void __init paging_init(void)
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#ifdef CONFIG_PA20
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/*
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* Currently, all PA20 chips have 18 bit protection id's, which is the
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* Currently, all PA20 chips have 18 bit protection IDs, which is the
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* limiting factor (space ids are 32 bits).
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*/
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@ -899,10 +899,10 @@ void __init paging_init(void)
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#else
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/*
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* Currently we have a one-to-one relationship between space id's and
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* protection id's. Older parisc chips (PCXS, PCXT, PCXL, PCXL2) only
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* support 15 bit protection id's, so that is the limiting factor.
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* PCXT' has 18 bit protection id's, but only 16 bit spaceids, so it's
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* Currently we have a one-to-one relationship between space IDs and
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* protection IDs. Older parisc chips (PCXS, PCXT, PCXL, PCXL2) only
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* support 15 bit protection IDs, so that is the limiting factor.
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* PCXT' has 18 bit protection IDs, but only 16 bit spaceids, so it's
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* probably not worth the effort for a special case here.
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*/
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