Documentation: amd-pstate: grammar and sentence structure updates
Signed-off-by: Jan Engelhardt <jengelh@inai.de> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Jan Engelhardt
Rafael J. Wysocki
parent
895519c19f
commit
7000ef3805
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@ -19,7 +19,7 @@ Linux kernel. The new mechanism is based on Collaborative Processor
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Performance Control (CPPC) which provides finer grain frequency management
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than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
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the ACPI P-states driver to manage CPU frequency and clocks with switching
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only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a
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only in 3 P-states. CPPC replaces the ACPI P-states controls and allows a
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flexible, low-latency interface for the Linux kernel to directly
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communicate the performance hints to hardware.
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@ -27,7 +27,7 @@ communicate the performance hints to hardware.
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``ondemand``, etc. to manage the performance hints which are provided by
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CPPC hardware functionality that internally follows the hardware
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specification (for details refer to AMD64 Architecture Programmer's Manual
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Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic
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Volume 2: System Programming [1]_). Currently, ``amd-pstate`` supports basic
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frequency control function according to kernel governors on some of the
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Zen2 and Zen3 processors, and we will implement more AMD specific functions
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in future after we verify them on the hardware and SBIOS.
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@ -41,9 +41,9 @@ continuous, abstract, and unit-less performance value in a scale that is
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not tied to a specific performance state / frequency. This is an ACPI
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standard [2]_ which software can specify application performance goals and
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hints as a relative target to the infrastructure limits. AMD processors
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provides the low latency register model (MSR) instead of AML code
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provide the low latency register model (MSR) instead of an AML code
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interpreter for performance adjustments. ``amd-pstate`` will initialize a
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``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks
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``struct cpufreq_driver`` instance, ``amd_pstate_driver``, with the callbacks
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to manage each performance update behavior. ::
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Highest Perf ------>+-----------------------+ +-----------------------+
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@ -91,26 +91,26 @@ AMD CPPC Performance Capability
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Highest Performance (RO)
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.........................
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It is the absolute maximum performance an individual processor may reach,
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This is the absolute maximum performance an individual processor may reach,
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assuming ideal conditions. This performance level may not be sustainable
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for long durations and may only be achievable if other platform components
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are in a specific state; for example, it may require other processors be in
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are in a specific state; for example, it may require other processors to be in
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an idle state. This would be equivalent to the highest frequencies
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supported by the processor.
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Nominal (Guaranteed) Performance (RO)
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......................................
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It is the maximum sustained performance level of the processor, assuming
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ideal operating conditions. In absence of an external constraint (power,
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thermal, etc.) this is the performance level the processor is expected to
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This is the maximum sustained performance level of the processor, assuming
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ideal operating conditions. In the absence of an external constraint (power,
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thermal, etc.), this is the performance level the processor is expected to
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be able to maintain continuously. All cores/processors are expected to be
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able to sustain their nominal performance state simultaneously.
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Lowest non-linear Performance (RO)
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...................................
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It is the lowest performance level at which nonlinear power savings are
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This is the lowest performance level at which nonlinear power savings are
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achieved, for example, due to the combined effects of voltage and frequency
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scaling. Above this threshold, lower performance levels should be generally
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more energy efficient than higher performance levels. This register
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@ -119,7 +119,7 @@ effectively conveys the most efficient performance level to ``amd-pstate``.
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Lowest Performance (RO)
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........................
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It is the absolute lowest performance level of the processor. Selecting a
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This is the absolute lowest performance level of the processor. Selecting a
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performance level lower than the lowest nonlinear performance level may
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cause an efficiency penalty but should reduce the instantaneous power
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consumption of the processor.
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@ -149,14 +149,14 @@ a relative number. This can be expressed as percentage of nominal
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performance (infrastructure max). Below the nominal sustained performance
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level, desired performance expresses the average performance level of the
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processor subject to hardware. Above the nominal performance level,
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processor must provide at least nominal performance requested and go higher
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the processor must provide at least nominal performance requested and go higher
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if current operating conditions allow.
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Energy Performance Preference (EPP) (RW)
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.........................................
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Provides a hint to the hardware if software wants to bias toward performance
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(0x0) or energy efficiency (0xff).
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This attribute provides a hint to the hardware if software wants to bias
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toward performance (0x0) or energy efficiency (0xff).
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Key Governors Support
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@ -173,35 +173,34 @@ operating frequencies supported by the hardware. Users can check the
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``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic
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frequency control. It is to fine tune the processor configuration on
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``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate``
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registers adjust_perf callback to implement the CPPC similar performance
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update behavior. It is initialized by ``sugov_start`` and then populate the
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CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as
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the utilization update callback function in CPU scheduler. CPU scheduler
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will call ``cpufreq_update_util`` and assign the target performance
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according to the ``struct sugov_cpu`` that utilization update belongs to.
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Then ``amd-pstate`` updates the desired performance according to the CPU
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registers the adjust_perf callback to implement performance update behavior
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similar to CPPC. It is initialized by ``sugov_start`` and then populates the
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CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as the
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utilization update callback function in the CPU scheduler. The CPU scheduler
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will call ``cpufreq_update_util`` and assigns the target performance according
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to the ``struct sugov_cpu`` that the utilization update belongs to.
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Then, ``amd-pstate`` updates the desired performance according to the CPU
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scheduler assigned.
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Processor Support
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=======================
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The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is
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not existed at the detected processor, and it uses ``acpi_cpc_valid`` to
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check the _CPC existence. All Zen based processors support legacy ACPI
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hardware P-States function, so while the ``amd-pstate`` fails to be
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initialized, the kernel will fall back to initialize ``acpi-cpufreq``
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driver.
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The ``amd-pstate`` initialization will fail if the ``_CPC`` entry in the ACPI
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SBIOS does not exist in the detected processor. It uses ``acpi_cpc_valid``
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to check the existence of ``_CPC``. All Zen based processors support the legacy
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ACPI hardware P-States function, so when ``amd-pstate`` fails initialization,
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the kernel will fall back to initialize the ``acpi-cpufreq`` driver.
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There are two types of hardware implementations for ``amd-pstate``: one is
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`Full MSR Support <perf_cap_>`_ and another is `Shared Memory Support
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<perf_cap_>`_. It can use :c:macro:`X86_FEATURE_CPPC` feature flag (for
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details refer to Processor Programming Reference (PPR) for AMD Family
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19h Model 51h, Revision A1 Processors [3]_) to indicate the different
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types. ``amd-pstate`` is to register different ``static_call`` instances
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for different hardware implementations.
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<perf_cap_>`_. It can use the :c:macro:`X86_FEATURE_CPPC` feature flag to
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indicate the different types. (For details, refer to the Processor Programming
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Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors [3]_.)
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``amd-pstate`` is to register different ``static_call`` instances for different
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hardware implementations.
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Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the
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Currently, some of the Zen2 and Zen3 processors support ``amd-pstate``. In the
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future, it will be supported on more and more AMD processors.
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Full MSR Support
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@ -210,18 +209,18 @@ Full MSR Support
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Some new Zen3 processors such as Cezanne provide the MSR registers directly
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while the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is set.
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``amd-pstate`` can handle the MSR register to implement the fast switch
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function in ``CPUFreq`` that can shrink latency of frequency control on the
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interrupt context. The functions with ``pstate_xxx`` prefix represent the
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operations of MSR registers.
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function in ``CPUFreq`` that can reduce the latency of frequency control in
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interrupt context. The functions with a ``pstate_xxx`` prefix represent the
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operations on MSR registers.
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Shared Memory Support
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----------------------
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If :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, that means the
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processor supports shared memory solution. In this case, ``amd-pstate``
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If the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, the
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processor supports the shared memory solution. In this case, ``amd-pstate``
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uses the ``cppc_acpi`` helper methods to implement the callback functions
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that defined on ``static_call``. The functions with ``cppc_xxx`` prefix
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represent the operations of acpi cppc helpers for shared memory solution.
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that are defined on ``static_call``. The functions with the ``cppc_xxx`` prefix
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represent the operations of ACPI CPPC helpers for the shared memory solution.
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AMD P-States and ACPI hardware P-States always can be supported in one
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@ -234,7 +233,7 @@ User Space Interface in ``sysfs``
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==================================
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``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to
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control its functionality at the system level. They located in the
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control its functionality at the system level. They are located in the
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``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. ::
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root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd*
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@ -246,38 +245,38 @@ control its functionality at the system level. They located in the
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``amd_pstate_highest_perf / amd_pstate_max_freq``
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Maximum CPPC performance and CPU frequency that the driver is allowed to
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set in percent of the maximum supported CPPC performance level (the highest
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set, in percent of the maximum supported CPPC performance level (the highest
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performance supported in `AMD CPPC Performance Capability <perf_cap_>`_).
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In some of ASICs, the highest CPPC performance is not the one in the _CPC
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table, so we need to expose it to sysfs. If boost is not active but
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supported, this maximum frequency will be larger than the one in
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In some ASICs, the highest CPPC performance is not the one in the ``_CPC``
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table, so we need to expose it to sysfs. If boost is not active, but
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still supported, this maximum frequency will be larger than the one in
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``cpuinfo``.
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This attribute is read-only.
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``amd_pstate_lowest_nonlinear_freq``
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The lowest non-linear CPPC CPU frequency that the driver is allowed to set
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in percent of the maximum supported CPPC performance level (Please see the
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The lowest non-linear CPPC CPU frequency that the driver is allowed to set,
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in percent of the maximum supported CPPC performance level. (Please see the
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lowest non-linear performance in `AMD CPPC Performance Capability
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<perf_cap_>`_).
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<perf_cap_>`_.)
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This attribute is read-only.
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For other performance and frequency values, we can read them back from
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Other performance and frequency values can be read back from
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``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
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``amd-pstate`` vs ``acpi-cpufreq``
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======================================
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On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables
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provided by the platform firmware used for CPU performance scaling, but
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only provides 3 P-states on AMD processors.
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However, on modern AMD APU and CPU series, it provides the collaborative
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processor performance control according to ACPI protocol and customize this
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for AMD platforms. That is fine-grain and continuous frequency range
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On the majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables
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provided by the platform firmware are used for CPU performance scaling, but
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only provide 3 P-states on AMD processors.
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However, on modern AMD APU and CPU series, hardware provides the Collaborative
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Processor Performance Control according to the ACPI protocol and customizes this
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for AMD platforms. That is, fine-grained and continuous frequency ranges
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instead of the legacy hardware P-states. ``amd-pstate`` is the kernel
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module which supports the new AMD P-States mechanism on most of future AMD
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platforms. The AMD P-States mechanism will be the more performance and energy
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module which supports the new AMD P-States mechanism on most of the future AMD
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platforms. The AMD P-States mechanism is the more performance and energy
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efficiency frequency management method on AMD processors.
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Kernel Module Options for ``amd-pstate``
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@ -287,25 +286,25 @@ Kernel Module Options for ``amd-pstate``
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Use a module param (shared_mem) to enable related processors manually with
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**amd_pstate.shared_mem=1**.
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Due to the performance issue on the processors with `Shared Memory Support
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<perf_cap_>`_, so we disable it for the moment and will enable this by default
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once we address performance issue on this solution.
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<perf_cap_>`_, we disable it presently and will re-enable this by default
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once we address performance issue with this solution.
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The way to check whether current processor is `Full MSR Support <perf_cap_>`_
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To check whether the current processor is using `Full MSR Support <perf_cap_>`_
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or `Shared Memory Support <perf_cap_>`_ : ::
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ray@hr-test1:~$ lscpu | grep cppc
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Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
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If CPU Flags have cppc, then this processor supports `Full MSR Support
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<perf_cap_>`_. Otherwise it supports `Shared Memory Support <perf_cap_>`_.
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If the CPU flags have ``cppc``, then this processor supports `Full MSR Support
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<perf_cap_>`_. Otherwise, it supports `Shared Memory Support <perf_cap_>`_.
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``cpupower`` tool support for ``amd-pstate``
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===============================================
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``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency
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information. And it is in progress to support more and more operations for new
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``amd-pstate`` module with this tool. ::
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``amd-pstate`` is supported by the ``cpupower`` tool, which can be used to dump
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frequency information. Development is in progress to support more and more
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operations for the new ``amd-pstate`` module with this tool. ::
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root@hr-test1:/home/ray# cpupower frequency-info
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analyzing CPU 0:
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@ -336,10 +335,10 @@ Trace Events
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--------------
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There are two static trace events that can be used for ``amd-pstate``
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diagnostics. One of them is the cpu_frequency trace event generally used
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diagnostics. One of them is the ``cpu_frequency`` trace event generally used
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by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event
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specific to ``amd-pstate``. The following sequence of shell commands can
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be used to enable them and see their output (if the kernel is generally
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be used to enable them and see their output (if the kernel is
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configured to support event tracing). ::
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root@hr-test1:/home/ray# cd /sys/kernel/tracing/
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@ -364,7 +363,7 @@ configured to support event tracing). ::
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<idle>-0 [003] d.s.. 4995.980971: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=3 changed=false fast_switch=true
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<idle>-0 [011] d.s.. 4995.980996: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=11 changed=false fast_switch=true
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The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling
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The ``cpu_frequency`` trace event will be triggered either by the ``schedutil`` scaling
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governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the
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policies with other scaling governors).
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