bpf/tests: Add exhaustive tests of BPF_ATOMIC register combinations
This patch adds tests of all register combinations for BPF_ATOMIC operations on both BPF_W and BPF_DW sizes. Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20211001130348.3670534-9-johan.almbladh@anyfinetworks.com
This commit is contained in:
Johan Almbladh
Daniel Borkmann
parent
daed6083f4
commit
6fae2e8a1d
422
lib/test_bpf.c
422
lib/test_bpf.c
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@ -1805,6 +1805,246 @@ static int bpf_fill_cmpxchg32(struct bpf_test *self)
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&__bpf_emit_cmpxchg32);
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}
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/*
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* Test JITs that implement ATOMIC operations as function calls or
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* other primitives, and must re-arrange operands for argument passing.
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*/
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static int __bpf_fill_atomic_reg_pairs(struct bpf_test *self, u8 width, u8 op)
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{
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struct bpf_insn *insn;
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int len = 2 + 34 * 10 * 10;
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u64 mem, upd, res;
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int rd, rs, i = 0;
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insn = kmalloc_array(len, sizeof(*insn), GFP_KERNEL);
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if (!insn)
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return -ENOMEM;
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/* Operand and memory values */
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if (width == BPF_DW) {
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mem = 0x0123456789abcdefULL;
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upd = 0xfedcba9876543210ULL;
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} else { /* BPF_W */
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mem = 0x01234567U;
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upd = 0x76543210U;
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}
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/* Memory updated according to operation */
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switch (op) {
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case BPF_XCHG:
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res = upd;
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break;
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case BPF_CMPXCHG:
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res = mem;
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break;
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default:
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__bpf_alu_result(&res, mem, upd, BPF_OP(op));
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}
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/* Test all operand registers */
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for (rd = R0; rd <= R9; rd++) {
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for (rs = R0; rs <= R9; rs++) {
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u64 cmp, src;
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/* Initialize value in memory */
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i += __bpf_ld_imm64(&insn[i], R0, mem);
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insn[i++] = BPF_STX_MEM(width, R10, R0, -8);
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/* Initialize registers in order */
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i += __bpf_ld_imm64(&insn[i], R0, ~mem);
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i += __bpf_ld_imm64(&insn[i], rs, upd);
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insn[i++] = BPF_MOV64_REG(rd, R10);
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/* Perform atomic operation */
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insn[i++] = BPF_ATOMIC_OP(width, op, rd, rs, -8);
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if (op == BPF_CMPXCHG && width == BPF_W)
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insn[i++] = BPF_ZEXT_REG(R0);
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/* Check R0 register value */
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if (op == BPF_CMPXCHG)
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cmp = mem; /* Expect value from memory */
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else if (R0 == rd || R0 == rs)
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cmp = 0; /* Aliased, checked below */
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else
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cmp = ~mem; /* Expect value to be preserved */
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if (cmp) {
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insn[i++] = BPF_JMP32_IMM(BPF_JEQ, R0,
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(u32)cmp, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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insn[i++] = BPF_ALU64_IMM(BPF_RSH, R0, 32);
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insn[i++] = BPF_JMP32_IMM(BPF_JEQ, R0,
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cmp >> 32, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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}
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/* Check source register value */
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if (rs == R0 && op == BPF_CMPXCHG)
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src = 0; /* Aliased with R0, checked above */
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else if (rs == rd && (op == BPF_CMPXCHG ||
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!(op & BPF_FETCH)))
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src = 0; /* Aliased with rd, checked below */
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else if (op == BPF_CMPXCHG)
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src = upd; /* Expect value to be preserved */
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else if (op & BPF_FETCH)
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src = mem; /* Expect fetched value from mem */
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else /* no fetch */
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src = upd; /* Expect value to be preserved */
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if (src) {
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insn[i++] = BPF_JMP32_IMM(BPF_JEQ, rs,
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(u32)src, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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insn[i++] = BPF_ALU64_IMM(BPF_RSH, rs, 32);
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insn[i++] = BPF_JMP32_IMM(BPF_JEQ, rs,
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src >> 32, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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}
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/* Check destination register value */
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if (!(rd == R0 && op == BPF_CMPXCHG) &&
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!(rd == rs && (op & BPF_FETCH))) {
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insn[i++] = BPF_JMP_REG(BPF_JEQ, rd, R10, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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}
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/* Check value in memory */
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if (rs != rd) { /* No aliasing */
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i += __bpf_ld_imm64(&insn[i], R1, res);
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} else if (op == BPF_XCHG) { /* Aliased, XCHG */
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insn[i++] = BPF_MOV64_REG(R1, R10);
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} else if (op == BPF_CMPXCHG) { /* Aliased, CMPXCHG */
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i += __bpf_ld_imm64(&insn[i], R1, mem);
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} else { /* Aliased, ALU oper */
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i += __bpf_ld_imm64(&insn[i], R1, mem);
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insn[i++] = BPF_ALU64_REG(BPF_OP(op), R1, R10);
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}
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insn[i++] = BPF_LDX_MEM(width, R0, R10, -8);
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if (width == BPF_DW)
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insn[i++] = BPF_JMP_REG(BPF_JEQ, R0, R1, 2);
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else /* width == BPF_W */
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insn[i++] = BPF_JMP32_REG(BPF_JEQ, R0, R1, 2);
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insn[i++] = BPF_MOV32_IMM(R0, __LINE__);
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insn[i++] = BPF_EXIT_INSN();
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}
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}
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insn[i++] = BPF_MOV64_IMM(R0, 1);
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insn[i++] = BPF_EXIT_INSN();
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self->u.ptr.insns = insn;
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self->u.ptr.len = i;
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BUG_ON(i > len);
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return 0;
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}
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/* 64-bit atomic register tests */
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static int bpf_fill_atomic64_add_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_ADD);
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}
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static int bpf_fill_atomic64_and_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_AND);
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}
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static int bpf_fill_atomic64_or_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_OR);
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}
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static int bpf_fill_atomic64_xor_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_XOR);
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}
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static int bpf_fill_atomic64_add_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_ADD | BPF_FETCH);
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}
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static int bpf_fill_atomic64_and_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_AND | BPF_FETCH);
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}
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static int bpf_fill_atomic64_or_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_OR | BPF_FETCH);
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}
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static int bpf_fill_atomic64_xor_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_XOR | BPF_FETCH);
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}
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static int bpf_fill_atomic64_xchg_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_XCHG);
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}
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static int bpf_fill_atomic64_cmpxchg_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_DW, BPF_CMPXCHG);
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}
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/* 32-bit atomic register tests */
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static int bpf_fill_atomic32_add_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_ADD);
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}
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static int bpf_fill_atomic32_and_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_AND);
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}
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static int bpf_fill_atomic32_or_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_OR);
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}
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static int bpf_fill_atomic32_xor_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_XOR);
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}
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static int bpf_fill_atomic32_add_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_ADD | BPF_FETCH);
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}
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static int bpf_fill_atomic32_and_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_AND | BPF_FETCH);
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}
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static int bpf_fill_atomic32_or_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_OR | BPF_FETCH);
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}
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static int bpf_fill_atomic32_xor_fetch_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_XOR | BPF_FETCH);
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}
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static int bpf_fill_atomic32_xchg_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_XCHG);
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}
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static int bpf_fill_atomic32_cmpxchg_reg_pairs(struct bpf_test *self)
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{
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return __bpf_fill_atomic_reg_pairs(self, BPF_W, BPF_CMPXCHG);
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}
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/*
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* Test the two-instruction 64-bit immediate load operation for all
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* power-of-two magnitudes of the immediate operand. For each MSB, a block
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@ -11976,6 +12216,188 @@ static struct bpf_test tests[] = {
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{ { 0, 1 } },
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.fill_helper = bpf_fill_ld_imm64,
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},
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/* 64-bit ATOMIC register combinations */
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{
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"ATOMIC_DW_ADD: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_add_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_AND: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_and_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_OR: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_or_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_XOR: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_xor_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_ADD_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_add_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_AND_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_and_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_OR_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_or_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_XOR_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_xor_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_XCHG: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_xchg_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_DW_CMPXCHG: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic64_cmpxchg_reg_pairs,
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.stack_depth = 8,
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},
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/* 32-bit ATOMIC register combinations */
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{
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"ATOMIC_W_ADD: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_add_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_AND: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_and_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_OR: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_or_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_XOR: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_xor_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_ADD_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_add_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_AND_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_and_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_OR_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_or_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_XOR_FETCH: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_xor_fetch_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_XCHG: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_xchg_reg_pairs,
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.stack_depth = 8,
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},
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{
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"ATOMIC_W_CMPXCHG: register combinations",
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{ },
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INTERNAL,
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{ },
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{ { 0, 1 } },
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.fill_helper = bpf_fill_atomic32_cmpxchg_reg_pairs,
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.stack_depth = 8,
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},
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/* 64-bit ATOMIC magnitudes */
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{
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"ATOMIC_DW_ADD: all operand magnitudes",
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