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drm/i915: Don't do PM5/DDR DVFS with multiple pipes 

Enabling PM5/DDR DVFS with multiple active pipes isn't a validated
configuration. It does seem to work most of the time at least, but
there is clearly an additional risk of underruns, so let's not play
with fire.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-06-24 22:00:08 +03:00 committed by Daniel Vetter
parent 852eb00dc4
commit 6f9c784b7e
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/intel_pm.c
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@ -1327,6 +1327,9 @@ static void vlv_merge_wm(struct drm_device *dev,
if (num_active_crtcs != 1)
wm->cxsr = false;
if (num_active_crtcs > 1)
wm->level = VLV_WM_LEVEL_PM2;
for_each_intel_crtc(dev, crtc) {
struct vlv_wm_state *wm_state = &crtc->wm_state;
enum pipe pipe = crtc->pipe;