ARM: S3C24XX: move s3c244x irq init to common irq code
Base for further modifications. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
ad38bdd15d
commit
6f8d7ea275
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@ -33,7 +33,7 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o
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obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
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obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o
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obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o
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obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o
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obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
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obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
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@ -1,142 +0,0 @@
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/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
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*
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* Copyright (c) 2003-2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/irq.h>
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/* camera irq */
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static void s3c_irq_demux_cam(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 11;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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generic_handle_irq(IRQ_S3C2440_CAM_C);
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}
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if (subsrc & 2) {
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generic_handle_irq(IRQ_S3C2440_CAM_P);
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}
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}
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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static void
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s3c_irq_cam_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
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}
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static void
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s3c_irq_cam_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CAM);
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}
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static void
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s3c_irq_cam_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
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}
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static struct irq_chip s3c_irq_cam = {
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.irq_mask = s3c_irq_cam_mask,
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.irq_unmask = s3c_irq_cam_unmask,
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.irq_ack = s3c_irq_cam_ack,
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};
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static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
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{
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unsigned int irqno;
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irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
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handle_level_irq);
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set_irq_flags(IRQ_NFCON, IRQF_VALID);
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/* add chained handler for camera */
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irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
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handle_level_irq);
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irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
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for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c_irq_cam,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct subsys_interface s3c2440_irq_interface = {
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.name = "s3c2440_irq",
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.subsys = &s3c2440_subsys,
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.add_dev = s3c244x_irq_add,
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};
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static int s3c2440_irq_init(void)
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{
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return subsys_interface_register(&s3c2440_irq_interface);
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}
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arch_initcall(s3c2440_irq_init);
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static struct subsys_interface s3c2442_irq_interface = {
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.name = "s3c2442_irq",
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.subsys = &s3c2442_subsys,
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.add_dev = s3c244x_irq_add,
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};
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static int s3c2442_irq_init(void)
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{
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return subsys_interface_register(&s3c2442_irq_interface);
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}
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arch_initcall(s3c2442_irq_init);
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@ -729,6 +729,111 @@ void __init s3c2416_init_irq(void)
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#endif
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#ifdef CONFIG_CPU_S3C244X
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/* camera irq */
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static void s3c_irq_demux_cam(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 11;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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generic_handle_irq(IRQ_S3C2440_CAM_C);
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}
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if (subsrc & 2) {
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generic_handle_irq(IRQ_S3C2440_CAM_P);
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}
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}
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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static void
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s3c_irq_cam_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
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}
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static void
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s3c_irq_cam_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CAM);
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}
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static void
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s3c_irq_cam_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
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}
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static struct irq_chip s3c_irq_cam = {
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.irq_mask = s3c_irq_cam_mask,
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.irq_unmask = s3c_irq_cam_unmask,
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.irq_ack = s3c_irq_cam_ack,
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};
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static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
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{
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unsigned int irqno;
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irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
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handle_level_irq);
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set_irq_flags(IRQ_NFCON, IRQF_VALID);
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/* add chained handler for camera */
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irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
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handle_level_irq);
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irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
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for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c_irq_cam,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static struct subsys_interface s3c2440_irq_interface = {
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.name = "s3c2440_irq",
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.subsys = &s3c2440_subsys,
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.add_dev = s3c244x_irq_add,
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};
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static int s3c2440_irq_init(void)
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{
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return subsys_interface_register(&s3c2440_irq_interface);
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}
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arch_initcall(s3c2440_irq_init);
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static struct subsys_interface s3c2442_irq_interface = {
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.name = "s3c2442_irq",
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.subsys = &s3c2442_subsys,
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.add_dev = s3c244x_irq_add,
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};
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static int s3c2442_irq_init(void)
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{
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return subsys_interface_register(&s3c2442_irq_interface);
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}
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arch_initcall(s3c2442_irq_init);
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#endif
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#ifdef CONFIG_CPU_S3C2443
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static struct s3c_irq_data init_s3c2443base[32] = {
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
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