thermal: tegra: combine sensor group-related data
Combine sensor group-related data structures into struct tegra_tsensor_group. This provides a single location for sensor group data storage. More sensor group data will be added in subsequent patches. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Wei Ni
Eduardo Valentin
parent
a4dff94ffd
commit
6f7e0d9d08
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@ -28,6 +28,7 @@
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#include <linux/thermal.h>
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#include <soc/tegra/fuse.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#define SENSOR_CONFIG0 0
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#define SENSOR_CONFIG0_STOP BIT(0)
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@ -48,12 +49,24 @@
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#define SENSOR_PDIV 0x1c0
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#define SENSOR_PDIV_T124 0x8888
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#define SENSOR_PDIV_CPU_MASK (0xf << 12)
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#define SENSOR_PDIV_GPU_MASK (0xf << 8)
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#define SENSOR_PDIV_MEM_MASK (0xf << 4)
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#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
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#define SENSOR_HOTSPOT_OFF 0x1c4
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#define SENSOR_HOTSPOT_OFF_T124 0x00060600
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#define SENSOR_TEMP1 0x1c8
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#define SENSOR_TEMP2 0x1cc
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#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
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#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
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#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
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#define SENSOR_TEMP1 0x1c8
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#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
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#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
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#define SENSOR_TEMP2 0x1cc
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#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
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#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
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#define SENSOR_TEMP_MASK 0xffff
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#define READBACK_VALUE_MASK 0xff00
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#define READBACK_VALUE_SHIFT 8
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#define READBACK_ADD_HALF BIT(7)
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@ -77,8 +90,36 @@
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#define NOMINAL_CALIB_FT_T124 105
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#define NOMINAL_CALIB_CP_T124 25
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/* get val from register(r) mask bits(m) */
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#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
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/* set val(v) to mask bits(m) of register(r) */
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#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
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(((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
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/**
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* struct tegra_tsensor_group - SOC_THERM sensor group data
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* @name: short name of the temperature sensor group
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* @id: numeric ID of the temperature sensor group
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* @sensor_temp_offset: offset of the SENSOR_TEMP* register
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* @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
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* @pdiv: the sensor count post-divider to use during runtime
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* @pdiv_ate: the sensor count post-divider used during automated test
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* @pdiv_mask: register bitfield mask for the PDIV field for this sensor
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* @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
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PLLX sensor group
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* @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
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*/
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struct tegra_tsensor_group {
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const char *name;
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u8 id;
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u16 sensor_temp_offset;
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u32 sensor_temp_mask;
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u32 pdiv, pdiv_ate, pdiv_mask;
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u32 pllx_hotspot_diff, pllx_hotspot_mask;
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};
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struct tegra_tsensor_configuration {
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u32 tall, tsample, tiddq_en, ten_count, pdiv, tsample_ate, pdiv_ate;
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u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
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};
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struct tegra_tsensor {
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@ -86,21 +127,74 @@ struct tegra_tsensor {
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u32 base, calib_fuse_offset;
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/* Correction values used to modify values read from calibration fuses */
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s32 fuse_corr_alpha, fuse_corr_beta;
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const struct tegra_tsensor_group *group;
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};
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struct tegra_thermctl_zone {
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void __iomem *reg;
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unsigned int shift;
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u32 mask;
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};
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static const struct tegra_tsensor_configuration t124_tsensor_config = {
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.tall = 16300,
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.tsample = 120,
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.tiddq_en = 1,
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.ten_count = 1,
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.pdiv = 8,
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.tsample = 120,
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.tsample_ate = 480,
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.pdiv_ate = 8
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_CPU,
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.name = "cpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_CPU_MASK,
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.pllx_hotspot_diff = 10,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_GPU,
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.name = "gpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_GPU_MASK,
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.pllx_hotspot_diff = 5,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
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.id = TEGRA124_SOCTHERM_SENSOR_PLLX,
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.name = "pll",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
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.pllx_hotspot_diff = 0,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
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};
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static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
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.id = TEGRA124_SOCTHERM_SENSOR_MEM,
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.name = "mem",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_MEM_MASK,
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};
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static const struct tegra_tsensor_group *
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tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
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&tegra124_tsensor_group_cpu,
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&tegra124_tsensor_group_gpu,
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&tegra124_tsensor_group_pll,
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&tegra124_tsensor_group_mem,
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};
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static const struct tegra_tsensor t124_tsensors[] = {
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@ -110,6 +204,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x098,
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.fuse_corr_alpha = 1135400,
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.fuse_corr_beta = -6266900,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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@ -117,6 +212,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x084,
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.fuse_corr_alpha = 1122220,
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.fuse_corr_beta = -5700700,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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@ -124,6 +220,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x088,
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.fuse_corr_alpha = 1127000,
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.fuse_corr_beta = -6768200,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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@ -131,6 +228,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x12c,
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.fuse_corr_alpha = 1110900,
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.fuse_corr_beta = -6232000,
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.group = &tegra124_tsensor_group_cpu,
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},
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{
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.config = &t124_tsensor_config,
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@ -138,6 +236,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x158,
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.fuse_corr_alpha = 1122300,
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.fuse_corr_beta = -5936400,
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.group = &tegra124_tsensor_group_mem,
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},
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{
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.config = &t124_tsensor_config,
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@ -145,6 +244,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x15c,
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.fuse_corr_alpha = 1145700,
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.fuse_corr_beta = -7124600,
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.group = &tegra124_tsensor_group_mem,
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},
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{
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.config = &t124_tsensor_config,
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@ -152,6 +252,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x154,
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.fuse_corr_alpha = 1120100,
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.fuse_corr_beta = -6000500,
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.group = &tegra124_tsensor_group_gpu,
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},
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{
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.config = &t124_tsensor_config,
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@ -159,6 +260,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
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.calib_fuse_offset = 0x160,
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.fuse_corr_alpha = 1106500,
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.fuse_corr_beta = -6729300,
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.group = &tegra124_tsensor_group_pll,
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},
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};
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@ -167,8 +269,6 @@ struct tegra_soctherm {
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struct clk *clock_tsensor;
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struct clk *clock_soctherm;
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void __iomem *regs;
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#define ZONE_NUMBER 4
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};
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struct tsensor_shared_calibration {
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@ -237,8 +337,8 @@ calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
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delta_sens = actual_tsensor_ft - actual_tsensor_cp;
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delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
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mult = sensor->config->pdiv * sensor->config->tsample_ate;
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div = sensor->config->tsample * sensor->config->pdiv_ate;
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mult = sensor->group->pdiv * sensor->config->tsample_ate;
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div = sensor->config->tsample * sensor->group->pdiv_ate;
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therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
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(s64) delta_sens * div);
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@ -311,7 +411,8 @@ static int tegra_thermctl_get_temp(void *data, int *out_temp)
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struct tegra_thermctl_zone *zone = data;
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u32 val;
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val = (readl(zone->reg) >> zone->shift) & SENSOR_TEMP_MASK;
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val = readl(zone->reg);
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val = REG_GET_MASK(val, zone->mask);
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*out_temp = translate_temp(val);
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return 0;
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@ -327,18 +428,6 @@ static const struct of_device_id tegra_soctherm_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
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struct thermctl_zone_desc {
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unsigned int offset;
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unsigned int shift;
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};
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static const struct thermctl_zone_desc t124_thermctl_temp_zones[] = {
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{ SENSOR_TEMP1, 16 },
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{ SENSOR_TEMP2, 16 },
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{ SENSOR_TEMP1, 0 },
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{ SENSOR_TEMP2, 0 }
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};
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static int tegra_soctherm_probe(struct platform_device *pdev)
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{
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struct tegra_soctherm *tegra;
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@ -349,6 +438,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
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int err;
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const struct tegra_tsensor *tsensors = t124_tsensors;
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const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
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tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
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if (!tegra)
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@ -408,7 +498,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
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/* Initialize thermctl sensors */
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for (i = 0; i < ZONE_NUMBER; ++i) {
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for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
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struct tegra_thermctl_zone *zone =
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devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
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if (!zone) {
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@ -416,10 +506,11 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
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goto disable_clocks;
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}
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zone->reg = tegra->regs + t124_thermctl_temp_zones[i].offset;
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zone->shift = t124_thermctl_temp_zones[i].shift;
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zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
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zone->mask = ttgs[i]->sensor_temp_mask;
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z = devm_thermal_zone_of_sensor_register(&pdev->dev, i, zone,
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z = devm_thermal_zone_of_sensor_register(&pdev->dev,
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ttgs[i]->id, zone,
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&tegra_of_thermal_ops);
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if (IS_ERR(z)) {
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err = PTR_ERR(z);
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@ -9,5 +9,6 @@
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#define TEGRA124_SOCTHERM_SENSOR_MEM 1
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#define TEGRA124_SOCTHERM_SENSOR_GPU 2
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#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
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#define TEGRA124_SOCTHERM_SENSOR_NUM 4
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#endif
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