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PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window 

Current code erroneously sets-up only the lower 32-bit CPU base address
in the  outbound window, which results in outbound transactions not
working in 64-bit platforms.

Fix it.

Fixes: 9af6bcb11e ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
This commit is contained in:
Hou Zhiqiang 2019-07-05 17:56:51 +08:00 committed by Lorenzo Pieralisi
parent 7717c7d7da
commit 6f7374b871
1 changed files with 4 additions and 1 deletions
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5
drivers/pci/controller/pcie-mobiveil.c
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@ -70,6 +70,7 @@
#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win) #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
#define AXI_WINDOW_ALIGN_MASK 3 #define AXI_WINDOW_ALIGN_MASK 3
@ -518,8 +519,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
* program AXI window base with appropriate value in * program AXI window base with appropriate value in
* PAB_AXI_AMAP_AXI_WIN0 register * PAB_AXI_AMAP_AXI_WIN0 register
*/ */
csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK), csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
PAB_AXI_AMAP_AXI_WIN(win_num)); PAB_AXI_AMAP_AXI_WIN(win_num));
csr_writel(pcie, upper_32_bits(cpu_addr),
PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
csr_writel(pcie, lower_32_bits(pci_addr), csr_writel(pcie, lower_32_bits(pci_addr),
PAB_AXI_AMAP_PEX_WIN_L(win_num)); PAB_AXI_AMAP_PEX_WIN_L(win_num));