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drm/amd/powerplay: add ECC feature bit 

It's OK to have this feature bit with old SMU firmwares.
But the feature should be disabled on them.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-03-23 01:02:44 +08:00 committed by Alex Deucher
parent ad51c46eec
commit 6f5d29ff1a
3 changed files with 12 additions and 2 deletions
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10
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
View File

@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
* MP0CLK DS * MP0CLK DS
*/ */
data->registry_data.disallowed_features = 0xE0041C00; data->registry_data.disallowed_features = 0xE0041C00;
/* ECC feature should be disabled on old SMUs */
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smum_get_argument(hwmgr);
if (hwmgr->smu_version < 0x282100)
data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
data->registry_data.od_state_in_dc_support = 0; data->registry_data.od_state_in_dc_support = 0;
data->registry_data.thermal_support = 1; data->registry_data.thermal_support = 1;
data->registry_data.skip_baco_hardware = 0; data->registry_data.skip_baco_hardware = 0;
@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT; data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT; data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT; data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
for (i = 0; i < GNLD_FEATURES_MAX; i++) { for (i = 0; i < GNLD_FEATURES_MAX; i++) {
data->smu_features[i].smu_feature_bitmap = data->smu_features[i].smu_feature_bitmap =
@ -3020,7 +3027,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
"FCLK_DS", "FCLK_DS",
"MP1CLK_DS", "MP1CLK_DS",
"MP0CLK_DS", "MP0CLK_DS",
"XGMI"}; "XGMI",
"ECC"};
static const char *output_title[] = { static const char *output_title[] = {
"FEATURES", "FEATURES",
"BITMASK", "BITMASK",

1
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
View File

@ -80,6 +80,7 @@ enum {
GNLD_DS_MP1CLK, GNLD_DS_MP1CLK,
GNLD_DS_MP0CLK, GNLD_DS_MP0CLK,
GNLD_XGMI, GNLD_XGMI,
GNLD_ECC,
GNLD_FEATURES_MAX GNLD_FEATURES_MAX
}; };

3
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
View File

@ -99,7 +99,7 @@
#define FEATURE_DS_MP1CLK_BIT 30 #define FEATURE_DS_MP1CLK_BIT 30
#define FEATURE_DS_MP0CLK_BIT 31 #define FEATURE_DS_MP0CLK_BIT 31
#define FEATURE_XGMI_BIT 32 #define FEATURE_XGMI_BIT 32
#define FEATURE_SPARE_33_BIT 33 #define FEATURE_ECC_BIT 33
#define FEATURE_SPARE_34_BIT 34 #define FEATURE_SPARE_34_BIT 34
#define FEATURE_SPARE_35_BIT 35 #define FEATURE_SPARE_35_BIT 35
#define FEATURE_SPARE_36_BIT 36 #define FEATURE_SPARE_36_BIT 36
@ -166,6 +166,7 @@
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT ) #define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002