clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main clock that is feeding the NAND IP and correct it's parent to be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -294,8 +294,12 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
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8, 0, 0, 0, 0, 0, 0},
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{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
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9, 0, 0, 0, 0, 0, 0},
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{ AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C,
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{ AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
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10, 0, 0, 0, 0, 0, 0},
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{ AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
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10, 0, 0, 0, 0, 0, 4},
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{ AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
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10, 0, 0, 0, 0, 0, 4},
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};
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static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
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