arm64: dts: rockchip: Add basic cpu frequencies for RK3368
This adds and enable the operating points that have been tested and are currently supported by the SoC. This also adds clocks for ARMCLKL and ARMCLKB. Signed-off-by: Romain Perier <romain.perier@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -113,7 +113,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>; /* min followed by max */
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};
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@ -122,6 +123,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu_l2: cpu@2 {
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@ -129,6 +132,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu_l3: cpu@3 {
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@ -136,6 +141,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu_b0: cpu@100 {
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@ -143,7 +150,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>; /* min followed by max */
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};
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@ -152,6 +160,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu_b2: cpu@102 {
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@ -159,6 +169,8 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu_b3: cpu@103 {
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@ -166,6 +178,62 @@
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cluster0_opp: opp-table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <40000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1025000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1125000>;
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};
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};
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cluster1_opp: opp-table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <40000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <975000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1050000>;
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};
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};
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