irqchip/gemini: Refactor Gemini driver to reflect Faraday origin
The Gemini irqchip turns out to be a standard IP component from Faraday Technology named FTINTC010 after some research and new information. - Rename the driver and all symbols to reflect the new information. - Add the new compatible string "faraday,ftintc010" - Create a Kconfig symbol CONFIG_FARADAY_FTINTC010 so that SoCs using this interrupt controller can easily select and reuse it instead of hardwiring it to ARCH_GEMINI I have created a separate patch to select the new Kconfig symbol from the Gemini machine, which will be merged through the ARM SoC tree. Cc: Greentime Hu <green.hu@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Linus Walleij
Marc Zyngier
parent
77a452551b
commit
6ee532e2fa
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@ -115,6 +115,12 @@ config DW_APB_ICTL
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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@ -6,7 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o
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obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
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obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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@ -0,0 +1,187 @@
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/*
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* irqchip for the Faraday Technology FTINTC010 Copyright (C) 2017 Linus
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* Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/irq.c
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/cpu.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define FT010_NUM_IRQS 32
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#define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00)
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#define FT010_IRQ_MASK(base_addr) (base_addr + 0x04)
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#define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08)
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#define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C)
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#define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10)
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#define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14)
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#define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20)
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#define FT010_FIQ_MASK(base_addr) (base_addr + 0x24)
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#define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28)
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#define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C)
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#define FT010_FIQ_POLARITY(base_addr) (base_addr + 0x30)
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#define FT010_FIQ_STATUS(base_addr) (base_addr + 0x34)
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/**
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* struct ft010_irq_data - irq data container for the Faraday IRQ controller
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* @base: memory offset in virtual memory
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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*/
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struct ft010_irq_data {
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void __iomem *base;
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struct irq_chip chip;
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struct irq_domain *domain;
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};
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static void ft010_irq_mask(struct irq_data *d)
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{
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struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(FT010_IRQ_MASK(f->base));
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mask &= ~BIT(irqd_to_hwirq(d));
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writel(mask, FT010_IRQ_MASK(f->base));
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}
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static void ft010_irq_unmask(struct irq_data *d)
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{
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struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(FT010_IRQ_MASK(f->base));
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mask |= BIT(irqd_to_hwirq(d));
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writel(mask, FT010_IRQ_MASK(f->base));
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}
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static void ft010_irq_ack(struct irq_data *d)
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{
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struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
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writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
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}
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static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger)
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{
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struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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u32 mode, polarity;
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mode = readl(FT010_IRQ_MODE(f->base));
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polarity = readl(FT010_IRQ_POLARITY(f->base));
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if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
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irq_set_handler_locked(d, handle_level_irq);
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/* Disable edge detection */
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mode &= ~BIT(offset);
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polarity &= ~BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_RISING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity |= BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity &= ~BIT(offset);
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} else {
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irq_set_handler_locked(d, handle_bad_irq);
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pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
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offset);
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}
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writel(mode, FT010_IRQ_MODE(f->base));
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writel(polarity, FT010_IRQ_POLARITY(f->base));
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return 0;
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}
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static struct irq_chip ft010_irq_chip = {
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.name = "FTINTC010",
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.irq_ack = ft010_irq_ack,
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.irq_mask = ft010_irq_mask,
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.irq_unmask = ft010_irq_unmask,
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.irq_set_type = ft010_irq_set_type,
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};
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/* Local static for the IRQ entry call */
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static struct ft010_irq_data firq;
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asmlinkage void __exception_irq_entry ft010_irqchip_handle_irq(struct pt_regs *regs)
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{
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struct ft010_irq_data *f = &firq;
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int irq;
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u32 status;
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while ((status = readl(FT010_IRQ_STATUS(f->base)))) {
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irq = ffs(status) - 1;
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handle_domain_irq(f->domain, irq, regs);
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}
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}
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static int ft010_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct ft010_irq_data *f = d->host_data;
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irq_set_chip_data(irq, f);
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/* All IRQs should set up their type, flags as bad by default */
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irq_set_chip_and_handler(irq, &ft010_irq_chip, handle_bad_irq);
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irq_set_probe(irq);
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return 0;
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}
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static void ft010_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops ft010_irqdomain_ops = {
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.map = ft010_irqdomain_map,
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.unmap = ft010_irqdomain_unmap,
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.xlate = irq_domain_xlate_onetwocell,
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};
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int __init ft010_of_init_irq(struct device_node *node,
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struct device_node *parent)
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{
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struct ft010_irq_data *f = &firq;
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/*
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* Disable the idle handler by default since it is buggy
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* For more info see arch/arm/mach-gemini/idle.c
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*/
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cpu_idle_poll_ctrl(true);
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f->base = of_iomap(node, 0);
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WARN(!f->base, "unable to map gemini irq registers\n");
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/* Disable all interrupts */
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writel(0, FT010_IRQ_MASK(f->base));
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writel(0, FT010_FIQ_MASK(f->base));
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f->domain = irq_domain_add_simple(node, FT010_NUM_IRQS, 0,
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&ft010_irqdomain_ops, f);
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set_handle_irq(ft010_irqchip_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
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ft010_of_init_irq);
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IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
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ft010_of_init_irq);
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@ -1,185 +0,0 @@
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/*
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* irqchip for the Cortina Systems Gemini Copyright (C) 2017 Linus
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* Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/irq.c
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/cpu.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define GEMINI_NUM_IRQS 32
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#define GEMINI_IRQ_SOURCE(base_addr) (base_addr + 0x00)
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#define GEMINI_IRQ_MASK(base_addr) (base_addr + 0x04)
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#define GEMINI_IRQ_CLEAR(base_addr) (base_addr + 0x08)
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#define GEMINI_IRQ_MODE(base_addr) (base_addr + 0x0C)
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#define GEMINI_IRQ_POLARITY(base_addr) (base_addr + 0x10)
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#define GEMINI_IRQ_STATUS(base_addr) (base_addr + 0x14)
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#define GEMINI_FIQ_SOURCE(base_addr) (base_addr + 0x20)
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#define GEMINI_FIQ_MASK(base_addr) (base_addr + 0x24)
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#define GEMINI_FIQ_CLEAR(base_addr) (base_addr + 0x28)
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#define GEMINI_FIQ_MODE(base_addr) (base_addr + 0x2C)
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#define GEMINI_FIQ_POLARITY(base_addr) (base_addr + 0x30)
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#define GEMINI_FIQ_STATUS(base_addr) (base_addr + 0x34)
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/**
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* struct gemini_irq_data - irq data container for the Gemini IRQ controller
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* @base: memory offset in virtual memory
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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*/
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struct gemini_irq_data {
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void __iomem *base;
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struct irq_chip chip;
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struct irq_domain *domain;
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};
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static void gemini_irq_mask(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(GEMINI_IRQ_MASK(g->base));
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mask &= ~BIT(irqd_to_hwirq(d));
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writel(mask, GEMINI_IRQ_MASK(g->base));
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}
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static void gemini_irq_unmask(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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unsigned int mask;
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mask = readl(GEMINI_IRQ_MASK(g->base));
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mask |= BIT(irqd_to_hwirq(d));
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writel(mask, GEMINI_IRQ_MASK(g->base));
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}
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static void gemini_irq_ack(struct irq_data *d)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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writel(BIT(irqd_to_hwirq(d)), GEMINI_IRQ_CLEAR(g->base));
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}
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static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger)
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{
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struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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u32 mode, polarity;
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mode = readl(GEMINI_IRQ_MODE(g->base));
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polarity = readl(GEMINI_IRQ_POLARITY(g->base));
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if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
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irq_set_handler_locked(d, handle_level_irq);
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/* Disable edge detection */
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mode &= ~BIT(offset);
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polarity &= ~BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_RISING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity |= BIT(offset);
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} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
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irq_set_handler_locked(d, handle_edge_irq);
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mode |= BIT(offset);
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polarity &= ~BIT(offset);
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} else {
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irq_set_handler_locked(d, handle_bad_irq);
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pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
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offset);
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}
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writel(mode, GEMINI_IRQ_MODE(g->base));
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writel(polarity, GEMINI_IRQ_POLARITY(g->base));
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return 0;
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}
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static struct irq_chip gemini_irq_chip = {
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.name = "GEMINI",
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.irq_ack = gemini_irq_ack,
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.irq_mask = gemini_irq_mask,
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.irq_unmask = gemini_irq_unmask,
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.irq_set_type = gemini_irq_set_type,
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};
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/* Local static for the IRQ entry call */
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static struct gemini_irq_data girq;
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asmlinkage void __exception_irq_entry gemini_irqchip_handle_irq(struct pt_regs *regs)
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{
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struct gemini_irq_data *g = &girq;
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int irq;
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u32 status;
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while ((status = readl(GEMINI_IRQ_STATUS(g->base)))) {
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irq = ffs(status) - 1;
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handle_domain_irq(g->domain, irq, regs);
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}
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}
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static int gemini_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct gemini_irq_data *g = d->host_data;
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irq_set_chip_data(irq, g);
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/* All IRQs should set up their type, flags as bad by default */
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irq_set_chip_and_handler(irq, &gemini_irq_chip, handle_bad_irq);
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irq_set_probe(irq);
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return 0;
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}
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static void gemini_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops gemini_irqdomain_ops = {
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.map = gemini_irqdomain_map,
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.unmap = gemini_irqdomain_unmap,
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.xlate = irq_domain_xlate_onetwocell,
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};
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int __init gemini_of_init_irq(struct device_node *node,
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struct device_node *parent)
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{
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struct gemini_irq_data *g = &girq;
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/*
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* Disable the idle handler by default since it is buggy
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* For more info see arch/arm/mach-gemini/idle.c
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*/
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cpu_idle_poll_ctrl(true);
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g->base = of_iomap(node, 0);
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WARN(!g->base, "unable to map gemini irq registers\n");
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/* Disable all interrupts */
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writel(0, GEMINI_IRQ_MASK(g->base));
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writel(0, GEMINI_FIQ_MASK(g->base));
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g->domain = irq_domain_add_simple(node, GEMINI_NUM_IRQS, 0,
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&gemini_irqdomain_ops, g);
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set_handle_irq(gemini_irqchip_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
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gemini_of_init_irq);
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