These changes add DT boot support to DaVinci DA850
SoC. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJQj6QrAAoJEGFBu2jqvgRNn0gQAIr9rITJ0pg5KdUNLdEZE2yE XjnkQWDF94KWvLhqj4rmYiPZDDCCaLSMgxbXizkJApmqwNeSX20MjeZmiURAXTva AFNVa7CAHtO7oXIgk9bhZkkFk+VFHuGRNHHjO1kLbMr/pmfYJ16rgN0PB+PM9AkG 7bWP5F7Fd9wVkB4fmdrvTV0JdC5NquSmGUwnEQ9BCPoP89X4Flk3bSx2l5Q0aYN2 PwxTBlDwxZ59yoC7XqoHfox14M6G+0qd48tsT8yCxIyKNh1tNA02B9VIK6GT0fVL Y0ya6SZBLDSDnRL3X9+NgGk9xdXDqRgEgLWsFulJrbB2RIBUzhZ/lVrusmYEhKLn cCLuxrDjJj6T97fKpd/ZX0GDxldaAogjhNFqzAYLYAiGauSie7AXh1dg9iw5nkpJ PV2FHpyWKShvhca5i+DlZbl4p4XohVp5H9v9gWuqSw68DTiT2qweq24g9n70279N rmyI8mBcKfj0x040FPTZCNGwcSOxLfH6Q38ZTDWrkGeJEaWRm0VRTzMX7/zDXDPN vy1cJdPmEXPUx6pmWhUN7dA25MOnsPOVpKpwB8bYBSWoPvj4navbw3S+YhoTS3G/ EJPvR0IpeiptLgBrOtUlqJrEPA2O3NEXqTeLD2y6DapMPInXw/Ta5l1B5XDd/a3V tkJZCkmgBpRTLuEYfG05 =/FbB -----END PGP SIGNATURE----- Merge tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci into next/dt From Sekhar Nori: These changes add DT boot support to DaVinci DA850 SoC. * tag 'davinci-for-v3.8/dt' of git://gitorious.org/linux-davinci/linux-davinci: ARM: davinci: da850: generate dtbs for da850 boards ARM: davinci: add support for am1808 based EnBW CMC board ARM: davinci: da850 evm: add DT data ARM: davinci: da850: add SoC DT data ARM: davinci: da850: add DT boot support ARM: davinci: da8xx: add DA850 PRUSS support ARM: davinci: add platform hook to fetch the SRAM pool ARM: davinci: da850: changed SRAM allocator to shared ram. ARM: davinci: sram: switch from iotable to ioremapped regions uio: uio_pruss: replace private SRAM API with genalloc ARM: davinci: serial: provide API to initialze UART clocks ARM: davinci: convert platform code to use clk_prepare/clk_unprepare Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
6ee052a38f
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@ -0,0 +1,17 @@
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Texas Instruments DaVinci Platforms Device Tree Bindings
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--------------------------------------------------------
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DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
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Required root node properties:
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- compatible = "ti,da850-evm", "ti,da850";
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EnBW AM1808 based CMC board
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Required root node properties:
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- compatible = "enbw,cmc", "ti,da850;
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Generic DaVinci Boards
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----------------------
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DA850/OMAP-L138/AM18x generic board
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Required root node properties:
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- compatible = "ti,da850";
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@ -911,6 +911,7 @@ config ARCH_DAVINCI
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select GENERIC_IRQ_CHIP
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select HAVE_IDE
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select NEED_MACH_GPIO_H
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select USE_OF
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select ZONE_DMA
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help
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Support for TI's DaVinci platform.
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@ -0,0 +1,30 @@
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/*
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* Device Tree for AM1808 EnBW CMC board
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*
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* Copyright 2012 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/include/ "da850.dtsi"
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/ {
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compatible = "enbw,cmc", "ti,da850";
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model = "EnBW CMC";
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soc {
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serial0: serial@1c42000 {
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status = "okay";
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};
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serial1: serial@1d0c000 {
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status = "okay";
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};
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serial2: serial@1d0d000 {
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status = "okay";
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};
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};
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};
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@ -0,0 +1,28 @@
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/*
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* Device Tree for DA850 EVM board
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, version 2.
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*/
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/dts-v1/;
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/include/ "da850.dtsi"
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/ {
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compatible = "ti,da850-evm", "ti,da850";
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model = "DA850/AM1808/OMAP-L138 EVM";
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soc {
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serial0: serial@1c42000 {
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status = "okay";
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};
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serial1: serial@1d0c000 {
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status = "okay";
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};
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serial2: serial@1d0d000 {
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status = "okay";
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};
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};
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};
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@ -0,0 +1,60 @@
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/*
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* Copyright 2012 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "skeleton.dtsi"
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/ {
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arm {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller {
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compatible = "ti,cp-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,intc-size = <100>;
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reg = <0xfffee000 0x2000>;
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};
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};
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soc {
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compatible = "simple-bus";
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model = "da850";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x01c00000 0x400000>;
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serial0: serial@1c42000 {
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compatible = "ns16550a";
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reg = <0x42000 0x100>;
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clock-frequency = <150000000>;
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reg-shift = <2>;
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interrupts = <25>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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serial1: serial@1d0c000 {
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compatible = "ns16550a";
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reg = <0x10c000 0x100>;
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clock-frequency = <150000000>;
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reg-shift = <2>;
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interrupts = <53>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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serial2: serial@1d0d000 {
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compatible = "ns16550a";
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reg = <0x10d000 0x100>;
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clock-frequency = <150000000>;
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reg-shift = <2>;
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interrupts = <61>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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};
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};
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@ -58,6 +58,14 @@ config ARCH_DAVINCI_TNETV107X
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comment "DaVinci Board Type"
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config MACH_DA8XX_DT
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bool "Support DA8XX platforms using device tree"
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default y
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depends on ARCH_DAVINCI_DA8XX
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help
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Say y here to include support for TI DaVinci DA850 based using
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Flattened Device Tree. More information at Documentation/devicetree
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config MACH_DAVINCI_EVM
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bool "TI DM644x EVM"
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default ARCH_DAVINCI_DM644x
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@ -22,6 +22,7 @@ obj-$(CONFIG_AINTC) += irq.o
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obj-$(CONFIG_CP_INTC) += cp_intc.o
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# Board specific
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obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
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obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
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obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
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@ -11,3 +11,5 @@ else
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params_phys-y := 0x80000100
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initrd_phys-y := 0x80800000
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endif
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dtb-$(CONFIG_MACH_DA8XX_DT) += da850-enbw-cmc.dtb da850-evm.dtb
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@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
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if (IS_ERR(aemif))
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WARN("%s: unable to get AEMIF clock\n", __func__);
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else
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clk_enable(aemif);
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clk_prepare_enable(aemif);
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platform_add_devices(davinci_evm_devices,
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ARRAY_SIZE(davinci_evm_devices));
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@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
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if (IS_ERR(aemif))
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WARN("%s: unable to get AEMIF clock\n", __func__);
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else
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clk_enable(aemif);
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clk_prepare_enable(aemif);
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platform_add_devices(davinci_leopard_devices,
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ARRAY_SIZE(davinci_leopard_devices));
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@ -478,7 +478,7 @@ static void __init evm_init_cpld(void)
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aemif_clk = clk_get(NULL, "aemif");
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if (IS_ERR(aemif_clk))
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return;
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clk_enable(aemif_clk);
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clk_prepare_enable(aemif_clk);
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if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
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"cpld") == NULL)
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@ -489,7 +489,7 @@ static void __init evm_init_cpld(void)
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SECTION_SIZE);
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fail:
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pr_err("ERROR: can't map CPLD\n");
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clk_disable(aemif_clk);
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clk_disable_unprepare(aemif_clk);
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return;
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}
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@ -776,7 +776,7 @@ static __init void davinci_evm_init(void)
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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aemif_clk = clk_get(NULL, "aemif");
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clk_enable(aemif_clk);
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clk_prepare_enable(aemif_clk);
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if (HAS_ATA) {
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if (HAS_NAND || HAS_NOR)
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@ -188,7 +188,7 @@ static __init void davinci_ntosd2_init(void)
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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aemif_clk = clk_get(NULL, "aemif");
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clk_enable(aemif_clk);
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clk_prepare_enable(aemif_clk);
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if (HAS_ATA) {
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if (HAS_NAND)
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@ -212,6 +212,12 @@ static struct clk tptc2_clk = {
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.flags = ALWAYS_ENABLED,
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};
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static struct clk pruss_clk = {
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.name = "pruss",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_PRUSS,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll0_sysclk2,
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@ -385,6 +391,7 @@ static struct clk_lookup da850_clks[] = {
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CLK(NULL, "tptc1", &tptc1_clk),
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CLK(NULL, "tpcc1", &tpcc1_clk),
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CLK(NULL, "tptc2", &tptc2_clk),
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CLK("pruss_uio", "pruss", &pruss_clk),
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CLK(NULL, "uart0", &uart0_clk),
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CLK(NULL, "uart1", &uart1_clk),
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CLK(NULL, "uart2", &uart2_clk),
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@ -781,12 +788,6 @@ static struct map_desc da850_io_desc[] = {
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.length = DA8XX_CP_INTC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = SRAM_VIRT,
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.pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE
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},
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};
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static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
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@ -1239,8 +1240,8 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
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.gpio_irq = IRQ_DA8XX_GPIO0,
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.serial_dev = &da8xx_serial_device,
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.emac_pdata = &da8xx_emac_pdata,
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.sram_dma = DA8XX_ARM_RAM_BASE,
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.sram_len = SZ_8K,
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.sram_dma = DA8XX_SHARED_RAM_BASE,
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.sram_len = SZ_128K,
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};
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void __init da850_init(void)
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@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Modified from mach-omap/omap2/board-generic.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/arch.h>
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#include <mach/common.h>
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#include <mach/cp_intc.h>
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#include <mach/da8xx.h>
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#define DA8XX_NUM_UARTS 3
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void __init da8xx_uart_clk_enable(void)
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{
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int i;
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for (i = 0; i < DA8XX_NUM_UARTS; i++)
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davinci_serial_setup_clk(i, NULL);
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}
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static struct of_device_id da8xx_irq_match[] __initdata = {
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{ .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
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{ }
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};
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static void __init da8xx_init_irq(void)
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{
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of_irq_init(da8xx_irq_match);
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}
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#ifdef CONFIG_ARCH_DAVINCI_DA850
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static void __init da850_init_machine(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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da8xx_uart_clk_enable();
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}
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static const char *da850_boards_compat[] __initdata = {
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"enbw,cmc",
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"ti,da850-evm",
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"ti,da850",
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NULL,
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};
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DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
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.map_io = da850_init,
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.init_irq = da8xx_init_irq,
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.timer = &davinci_timer,
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.init_machine = da850_init_machine,
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.dt_compat = da850_boards_compat,
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.init_late = davinci_init_late,
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.restart = da8xx_restart,
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MACHINE_END
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#endif
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@ -22,6 +22,7 @@
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#include <mach/time.h>
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#include <mach/da8xx.h>
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#include <mach/cpuidle.h>
|
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#include <mach/sram.h>
|
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|
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#include "clock.h"
|
||||
#include "asp.h"
|
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|
|
@ -32,6 +33,7 @@
|
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#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
|
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#define DA8XX_I2C0_BASE 0x01c22000
|
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#define DA8XX_RTC_BASE 0x01c23000
|
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#define DA8XX_PRUSS_MEM_BASE 0x01c30000
|
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#define DA8XX_MMCSD0_BASE 0x01c40000
|
||||
#define DA8XX_SPI0_BASE 0x01c41000
|
||||
#define DA830_SPI1_BASE 0x01e12000
|
||||
|
|
@ -518,6 +520,75 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
|
|||
}
|
||||
}
|
||||
|
||||
static struct resource da8xx_pruss_resources[] = {
|
||||
{
|
||||
.start = DA8XX_PRUSS_MEM_BASE,
|
||||
.end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT0,
|
||||
.end = IRQ_DA8XX_EVTOUT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT1,
|
||||
.end = IRQ_DA8XX_EVTOUT1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT2,
|
||||
.end = IRQ_DA8XX_EVTOUT2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT3,
|
||||
.end = IRQ_DA8XX_EVTOUT3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT4,
|
||||
.end = IRQ_DA8XX_EVTOUT4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT5,
|
||||
.end = IRQ_DA8XX_EVTOUT5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT6,
|
||||
.end = IRQ_DA8XX_EVTOUT6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT7,
|
||||
.end = IRQ_DA8XX_EVTOUT7,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
|
||||
.pintc_base = 0x4000,
|
||||
};
|
||||
|
||||
static struct platform_device da8xx_uio_pruss_dev = {
|
||||
.name = "pruss_uio",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(da8xx_pruss_resources),
|
||||
.resource = da8xx_pruss_resources,
|
||||
.dev = {
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &da8xx_uio_pruss_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
int __init da8xx_register_uio_pruss(void)
|
||||
{
|
||||
da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
|
||||
return platform_device_register(&da8xx_uio_pruss_dev);
|
||||
}
|
||||
|
||||
static const struct display_panel disp_panel = {
|
||||
QVGA,
|
||||
16,
|
||||
|
|
@ -900,7 +971,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
|
|||
if (IS_ERR(da850_sata_clk))
|
||||
return PTR_ERR(da850_sata_clk);
|
||||
|
||||
ret = clk_enable(da850_sata_clk);
|
||||
ret = clk_prepare_enable(da850_sata_clk);
|
||||
if (ret)
|
||||
goto err0;
|
||||
|
||||
|
|
@ -931,7 +1002,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
|
|||
return 0;
|
||||
|
||||
err1:
|
||||
clk_disable(da850_sata_clk);
|
||||
clk_disable_unprepare(da850_sata_clk);
|
||||
err0:
|
||||
clk_put(da850_sata_clk);
|
||||
return ret;
|
||||
|
|
@ -939,7 +1010,7 @@ err0:
|
|||
|
||||
static void da850_sata_exit(struct device *dev)
|
||||
{
|
||||
clk_disable(da850_sata_clk);
|
||||
clk_disable_unprepare(da850_sata_clk);
|
||||
clk_put(da850_sata_clk);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -758,12 +758,6 @@ static struct map_desc dm355_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
|
|
@ -985,12 +985,6 @@ static struct map_desc dm365_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource dm365_ks_resources[] = {
|
||||
|
|
|
|||
|
|
@ -786,12 +786,6 @@ static struct map_desc dm644x_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00008000),
|
||||
.length = SZ_16K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
|
|
@ -756,12 +756,6 @@ static struct map_desc dm646x_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
|
|
@ -104,8 +104,6 @@ int davinci_pm_init(void);
|
|||
static inline int davinci_pm_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
/* standard place to map on-chip SRAMs; they *may* support DMA */
|
||||
#define SRAM_VIRT 0xfffe0000
|
||||
#define SRAM_SIZE SZ_128K
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/platform_data/mmc-davinci.h>
|
||||
#include <linux/platform_data/usb-davinci.h>
|
||||
#include <linux/platform_data/spi-davinci.h>
|
||||
#include <linux/platform_data/uio_pruss.h>
|
||||
|
||||
#include <media/davinci/vpif_types.h>
|
||||
|
||||
|
|
@ -72,6 +73,7 @@ extern unsigned int da850_max_speed;
|
|||
#define DA8XX_AEMIF_CS2_BASE 0x60000000
|
||||
#define DA8XX_AEMIF_CS3_BASE 0x62000000
|
||||
#define DA8XX_AEMIF_CTL_BASE 0x68000000
|
||||
#define DA8XX_SHARED_RAM_BASE 0x80000000
|
||||
#define DA8XX_ARM_RAM_BASE 0xffff0000
|
||||
|
||||
void __init da830_init(void);
|
||||
|
|
@ -86,6 +88,7 @@ int da8xx_register_watchdog(void);
|
|||
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
|
||||
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
|
||||
int da8xx_register_emac(void);
|
||||
int da8xx_register_uio_pruss(void);
|
||||
int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
|
||||
int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
|
||||
int da850_register_mmcsd1(struct davinci_mmc_config *config);
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ struct davinci_uart_config {
|
|||
};
|
||||
|
||||
extern int davinci_serial_init(struct davinci_uart_config *);
|
||||
extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_SERIAL_H */
|
||||
|
|
|
|||
|
|
@ -24,4 +24,7 @@
|
|||
extern void *sram_alloc(size_t len, dma_addr_t *dma);
|
||||
extern void sram_free(void *addr, size_t len);
|
||||
|
||||
/* Get the struct gen_pool * for use in platform data */
|
||||
extern struct gen_pool *sram_get_gen_pool(void);
|
||||
|
||||
#endif /* __MACH_SRAM_H */
|
||||
|
|
|
|||
|
|
@ -70,11 +70,33 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
|
|||
UART_DM646X_SCR_TX_WATERMARK);
|
||||
}
|
||||
|
||||
/* Enable UART clock and obtain its rate */
|
||||
int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
|
||||
{
|
||||
char name[16];
|
||||
struct clk *clk;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
struct device *dev = &soc_info->serial_dev->dev;
|
||||
|
||||
sprintf(name, "uart%d", instance);
|
||||
clk = clk_get(dev, name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s:%d: failed to get UART%d clock\n",
|
||||
__func__, __LINE__, instance);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
if (rate)
|
||||
*rate = clk_get_rate(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init davinci_serial_init(struct davinci_uart_config *info)
|
||||
{
|
||||
int i;
|
||||
char name[16];
|
||||
struct clk *uart_clk;
|
||||
int i, ret;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
struct device *dev = &soc_info->serial_dev->dev;
|
||||
struct plat_serial8250_port *p = dev->platform_data;
|
||||
|
|
@ -87,16 +109,9 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
|
|||
if (!(info->enabled_uarts & (1 << i)))
|
||||
continue;
|
||||
|
||||
sprintf(name, "uart%d", i);
|
||||
uart_clk = clk_get(dev, name);
|
||||
if (IS_ERR(uart_clk)) {
|
||||
printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
|
||||
__func__, __LINE__, i);
|
||||
ret = davinci_serial_setup_clk(i, &p->uartclk);
|
||||
if (ret)
|
||||
continue;
|
||||
}
|
||||
|
||||
clk_enable(uart_clk);
|
||||
p->uartclk = clk_get_rate(uart_clk);
|
||||
|
||||
if (!p->membase && p->mapbase) {
|
||||
p->membase = ioremap(p->mapbase, SZ_4K);
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/genalloc.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
|
|
@ -17,6 +18,11 @@
|
|||
|
||||
static struct gen_pool *sram_pool;
|
||||
|
||||
struct gen_pool *sram_get_gen_pool(void)
|
||||
{
|
||||
return sram_pool;
|
||||
}
|
||||
|
||||
void *sram_alloc(size_t len, dma_addr_t *dma)
|
||||
{
|
||||
unsigned long vaddr;
|
||||
|
|
@ -32,7 +38,7 @@ void *sram_alloc(size_t len, dma_addr_t *dma)
|
|||
return NULL;
|
||||
|
||||
if (dma)
|
||||
*dma = dma_base + (vaddr - SRAM_VIRT);
|
||||
*dma = gen_pool_virt_to_phys(sram_pool, vaddr);
|
||||
return (void *)vaddr;
|
||||
|
||||
}
|
||||
|
|
@ -53,8 +59,10 @@ EXPORT_SYMBOL(sram_free);
|
|||
*/
|
||||
static int __init sram_init(void)
|
||||
{
|
||||
phys_addr_t phys = davinci_soc_info.sram_dma;
|
||||
unsigned len = davinci_soc_info.sram_len;
|
||||
int status = 0;
|
||||
void *addr;
|
||||
|
||||
if (len) {
|
||||
len = min_t(unsigned, len, SRAM_SIZE);
|
||||
|
|
@ -62,8 +70,17 @@ static int __init sram_init(void)
|
|||
if (!sram_pool)
|
||||
status = -ENOMEM;
|
||||
}
|
||||
if (sram_pool)
|
||||
status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
|
||||
|
||||
if (sram_pool) {
|
||||
addr = ioremap(phys, len);
|
||||
if (!addr)
|
||||
return -ENOMEM;
|
||||
status = gen_pool_add_virt(sram_pool, (unsigned)addr,
|
||||
phys, len, -1);
|
||||
if (status < 0)
|
||||
iounmap(addr);
|
||||
}
|
||||
|
||||
WARN_ON(status < 0);
|
||||
return status;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
|
|||
|
||||
timer_clk = clk_get(NULL, "timer0");
|
||||
BUG_ON(IS_ERR(timer_clk));
|
||||
clk_enable(timer_clk);
|
||||
clk_prepare_enable(timer_clk);
|
||||
|
||||
/* init timer hw */
|
||||
timer_init();
|
||||
|
|
@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
|
|||
wd_clk = clk_get(&pdev->dev, NULL);
|
||||
if (WARN_ON(IS_ERR(wd_clk)))
|
||||
return;
|
||||
clk_enable(wd_clk);
|
||||
clk_prepare_enable(wd_clk);
|
||||
|
||||
/* disable, internal clock source */
|
||||
__raw_writel(0, base + TCR);
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ config UIO_NETX
|
|||
config UIO_PRUSS
|
||||
tristate "Texas Instruments PRUSS driver"
|
||||
depends on ARCH_DAVINCI_DA850
|
||||
select GENERIC_ALLOCATOR
|
||||
help
|
||||
PRUSS driver for OMAPL138/DA850/AM18XX devices
|
||||
PRUSS driver requires user space components, examples and user space
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/slab.h>
|
||||
#include <mach/sram.h>
|
||||
#include <linux/genalloc.h>
|
||||
|
||||
#define DRV_NAME "pruss_uio"
|
||||
#define DRV_VERSION "1.0"
|
||||
|
|
@ -65,10 +65,11 @@ struct uio_pruss_dev {
|
|||
dma_addr_t sram_paddr;
|
||||
dma_addr_t ddr_paddr;
|
||||
void __iomem *prussio_vaddr;
|
||||
void *sram_vaddr;
|
||||
unsigned long sram_vaddr;
|
||||
void *ddr_vaddr;
|
||||
unsigned int hostirq_start;
|
||||
unsigned int pintc_base;
|
||||
struct gen_pool *sram_pool;
|
||||
};
|
||||
|
||||
static irqreturn_t pruss_handler(int irq, struct uio_info *info)
|
||||
|
|
@ -106,7 +107,9 @@ static void pruss_cleanup(struct platform_device *dev,
|
|||
gdev->ddr_paddr);
|
||||
}
|
||||
if (gdev->sram_vaddr)
|
||||
sram_free(gdev->sram_vaddr, sram_pool_sz);
|
||||
gen_pool_free(gdev->sram_pool,
|
||||
gdev->sram_vaddr,
|
||||
sram_pool_sz);
|
||||
kfree(gdev->info);
|
||||
clk_put(gdev->pruss_clk);
|
||||
kfree(gdev);
|
||||
|
|
@ -152,10 +155,17 @@ static int __devinit pruss_probe(struct platform_device *dev)
|
|||
goto out_free;
|
||||
}
|
||||
|
||||
gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr));
|
||||
if (!gdev->sram_vaddr) {
|
||||
dev_err(&dev->dev, "Could not allocate SRAM pool\n");
|
||||
goto out_free;
|
||||
if (pdata->sram_pool) {
|
||||
gdev->sram_pool = pdata->sram_pool;
|
||||
gdev->sram_vaddr =
|
||||
gen_pool_alloc(gdev->sram_pool, sram_pool_sz);
|
||||
if (!gdev->sram_vaddr) {
|
||||
dev_err(&dev->dev, "Could not allocate SRAM pool\n");
|
||||
goto out_free;
|
||||
}
|
||||
gdev->sram_paddr =
|
||||
gen_pool_virt_to_phys(gdev->sram_pool,
|
||||
gdev->sram_vaddr);
|
||||
}
|
||||
|
||||
gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
/* To configure the PRUSS INTC base offset for UIO driver */
|
||||
struct uio_pruss_pdata {
|
||||
u32 pintc_base;
|
||||
u32 pintc_base;
|
||||
struct gen_pool *sram_pool;
|
||||
};
|
||||
#endif /* _UIO_PRUSS_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue