b43: rename host flags defines
There are more than 3 registers on new hardware. Host flags handling has to be rewritten, as we can't use u128 type to handle all 5 regs. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -241,16 +241,18 @@ enum {
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#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
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#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
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#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
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#define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
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#define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */
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#define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */
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#define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */
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#define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */
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#define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */
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#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
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#define B43_SHM_SH_RADAR 0x0066 /* Radar register */
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#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
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#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
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#define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */
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#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
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#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
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#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
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#define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */
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#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
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/* TSSI information */
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#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
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@ -533,11 +533,11 @@ u64 b43_hf_read(struct b43_wldev *dev)
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{
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u64 ret;
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ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
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ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
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ret <<= 16;
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ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
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ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
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ret <<= 16;
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ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
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ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
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return ret;
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}
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@ -550,9 +550,9 @@ void b43_hf_write(struct b43_wldev *dev, u64 value)
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lo = (value & 0x00000000FFFFULL);
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mi = (value & 0x0000FFFF0000ULL) >> 16;
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hi = (value & 0xFFFF00000000ULL) >> 32;
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
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}
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/* Read the firmware capabilities bitmask (Opensource firmware only) */
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@ -428,7 +428,7 @@ int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
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average = (a + b + c + d + 2) / 4;
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if (is_ofdm) {
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/* Adjust for CCK-boost */
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if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
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if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
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& B43_HF_CCKBOOST)
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average = (average >= 13) ? (average - 13) : 0;
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}
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