drm/msm/dsi: inline msm_dsi_phy_set_src_pll
The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210331105735.3690009-24-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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001d8dc338
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6e2ad9c3bf
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@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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return 0;
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return 0;
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}
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}
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask)
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{
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int phy_id = phy->id;
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u32 val;
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if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
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return;
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val = dsi_phy_read(phy->base + reg);
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if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
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dsi_phy_write(phy->base + reg, val | bit_mask);
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else
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dsi_phy_write(phy->base + reg, val & (~bit_mask));
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}
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static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
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static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
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{
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{
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struct regulator_bulk_data *s = phy->supplies;
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struct regulator_bulk_data *s = phy->supplies;
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@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg {
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unsigned long min_pll_rate;
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unsigned long min_pll_rate;
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unsigned long max_pll_rate;
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unsigned long max_pll_rate;
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/*
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* Each cell {phy_id, pll_id} of the truth table indicates
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* if the source PLL selection bit should be set for each PHY.
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* Fill default H/W values in illegal cells, eg. cell {0, 1}.
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*/
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bool src_pll_truthtable[DSI_MAX][DSI_MAX];
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const resource_size_t io_start[DSI_MAX];
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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const int num_dsi_phy;
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const int quirks;
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const int quirks;
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@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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struct msm_dsi_phy_clk_request *clk_req);
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask);
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#endif /* __DSI_PHY_H__ */
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#endif /* __DSI_PHY_H__ */
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@ -921,7 +921,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -943,7 +942,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
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};
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};
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const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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int ret;
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int ret;
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void __iomem *base = phy->base;
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void __iomem *base = phy->base;
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void __iomem *lane_base = phy->lane_base;
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void __iomem *lane_base = phy->lane_base;
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u32 glbl_test_ctrl;
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if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
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if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
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DRM_DEV_ERROR(&phy->pdev->dev,
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DRM_DEV_ERROR(&phy->pdev->dev,
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@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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udelay(100);
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udelay(100);
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dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
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dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
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msm_dsi_phy_set_src_pll(phy, src_pll_id,
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glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
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REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
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if (phy->id == DSI_1 && src_pll_id == DSI_0)
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DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
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glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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else
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glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
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ret = dsi_14nm_set_usecase(phy);
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ret = dsi_14nm_set_usecase(phy);
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if (ret) {
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if (ret) {
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DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
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DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
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@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
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};
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};
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const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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int i;
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int i;
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void __iomem *base = phy->base;
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void __iomem *base = phy->base;
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u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
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u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
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u32 val;
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DBG("");
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DBG("");
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@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
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msm_dsi_phy_set_src_pll(phy, src_pll_id,
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val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
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REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
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if (src_pll_id == DSI_1)
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DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
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val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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else
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val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
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@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
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.src_pll_truthtable = { {false, true}, {false, true} },
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.has_phy_regulator = true,
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.has_phy_regulator = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 2,
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.num = 2,
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@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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struct msm_dsi_dphy_timing *timing = &phy->timing;
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struct msm_dsi_dphy_timing *timing = &phy->timing;
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int i;
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int i;
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void __iomem *base = phy->base;
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void __iomem *base = phy->base;
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u32 val;
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DBG("");
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DBG("");
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@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
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dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
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msm_dsi_phy_set_src_pll(phy, src_pll_id,
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val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
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REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
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if (phy->id == DSI_1 && src_pll_id == DSI_0)
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DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
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val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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else
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val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
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return 0;
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return 0;
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}
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}
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@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
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.src_pll_truthtable = { {true, true}, {false, true} },
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.has_phy_regulator = true,
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.has_phy_regulator = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
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};
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};
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const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
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.src_pll_truthtable = { {true, true}, {false, true} },
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.has_phy_regulator = true,
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.has_phy_regulator = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
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};
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};
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const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
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.src_pll_truthtable = { {true, true}, {true, true} },
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.has_phy_regulator = true,
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.has_phy_regulator = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
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.src_pll_truthtable = { {true, true}, {false, true} },
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.has_phy_regulator = true,
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.has_phy_regulator = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -957,7 +957,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
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}
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}
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const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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@ -980,7 +979,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
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};
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};
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const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
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const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
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.src_pll_truthtable = { {false, false}, {true, false} },
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.has_phy_lane = true,
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.has_phy_lane = true,
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.reg_cfg = {
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.reg_cfg = {
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.num = 1,
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.num = 1,
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