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ARM: dts: imx6qdl-wandboard: Let the codec control MCLK pinctrl 

sgtl5000 codec needs MCLK clock to be present so that it can
successfully read/write via I2C.

In the case of wandboard, MCLK is provided via
MX6QDL_PAD_GPIO_0__CCM_CLKO1 pad.

Move the MCLK pinctrl from hog group to the codec group, so that the
codec clock can be present prior to reading the codec ID.

This avoids the following error that happens from time to time:

[    2.484443] sgtl5000 1-000a: Error reading chip id -6

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam 2018-03-14 17:36:26 -03:00 committed by Shawn Guo
parent f9d7af0752
commit 6e1386b2ee
4 changed files with 8 additions and 3 deletions
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1
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
View File

@ -17,7 +17,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */

1
arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
View File

@ -17,7 +17,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */

1
arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
View File

@ -147,7 +147,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */

8
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -83,6 +83,8 @@
status = "okay";
codec: sgtl5000@a {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mclk>;
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
@ -142,6 +144,12 @@
>;
};
pinctrl_mclk: mclkgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0