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drm/amdgpu: Update umc v8_10_0 headers 

Add GeccCtrl offset and mask to umc v8_10_0 headers.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Candice Li 2022-09-26 16:18:56 +08:00 committed by Alex Deucher
parent 38dbbfa57c
commit 6dddc1eb96
2 changed files with 5 additions and 0 deletions
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2
drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_offset.h
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@ -29,5 +29,7 @@
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 2
#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 2
#define regUMCCH0_0_GeccCtrl 0x0053
#define regUMCCH0_0_GeccCtrl_BASE_IDX 2
#endif

3
drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_sh_mask.h
View File

@ -90,5 +90,8 @@
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
//UMCCH0_0_GeccCtrl
#define UMCCH0_0_GeccCtrl__UCFatalEn__SHIFT 0xd
#define UMCCH0_0_GeccCtrl__UCFatalEn_MASK 0x00002000L
#endif