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drm/nouveau/mmu: switch to instanced constructor 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 12:34:27 +10:00
parent 209ec1b841
commit 6dd123ba8a
22 changed files with 162 additions and 150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_mmu *mmu;
struct nvkm_subdev *mxm;
struct nvkm_pci *pci;
struct nvkm_pmu *pmu;
@ -131,7 +130,6 @@ struct nvkm_device_chip {
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
int (*pci )(struct nvkm_device *, int idx, struct nvkm_pci **);
int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -10,6 +10,7 @@ NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BUS , struct nvkm_bus , bus)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_INSTMEM , struct nvkm_instmem , imem)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FB , struct nvkm_fb , fb)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_LTC , struct nvkm_ltc , ltc)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_MMU , struct nvkm_mmu , mmu)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BAR , struct nvkm_bar , bar)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FAULT , struct nvkm_fault , fault)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ACR , struct nvkm_acr , acr)

30
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View File

@ -122,19 +122,19 @@ struct nvkm_mmu {
struct nvkm_device_oclass user;
};
int nv04_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int g84_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int mcp77_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gk104_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gk20a_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gm200_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gm20b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gp100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gp10b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gv100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int tu102_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv04_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int nv41_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int nv44_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int nv50_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int g84_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int mcp77_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gf100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gk104_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gk20a_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gm200_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gm20b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gp100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gp10b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int gv100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
int tu102_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_SUBDEV_MMU ] = "mmu",
[NVKM_SUBDEV_MXM ] = "mxm",
[NVKM_SUBDEV_PCI ] = "pci",
[NVKM_SUBDEV_PMU ] = "pmu",

175
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -85,7 +85,7 @@ nv4_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv04_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -106,7 +106,7 @@ nv5_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv04_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -128,7 +128,7 @@ nv10_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv04_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -148,7 +148,7 @@ nv11_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv11_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -170,7 +170,7 @@ nv15_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv04_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -192,7 +192,7 @@ nv17_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -214,7 +214,7 @@ nv18_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -236,7 +236,7 @@ nv1a_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv04_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -258,7 +258,7 @@ nv1f_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -280,7 +280,7 @@ nv20_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -302,7 +302,7 @@ nv25_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -324,7 +324,7 @@ nv28_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -346,7 +346,7 @@ nv2a_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -368,7 +368,7 @@ nv30_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -390,7 +390,7 @@ nv31_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -413,7 +413,7 @@ nv34_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -436,7 +436,7 @@ nv35_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -458,7 +458,7 @@ nv36_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv04_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv04_pci_new,
.timer = nv04_timer_new,
.disp = nv04_disp_new,
@ -481,7 +481,7 @@ nv40_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv40_timer_new,
@ -507,7 +507,7 @@ nv41_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -533,7 +533,7 @@ nv42_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -559,7 +559,7 @@ nv43_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -585,7 +585,7 @@ nv44_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -611,7 +611,7 @@ nv45_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -637,7 +637,7 @@ nv46_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv46_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -663,7 +663,7 @@ nv47_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -689,7 +689,7 @@ nv49_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -715,7 +715,7 @@ nv4a_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv04_mmu_new,
.mmu = { 0x00000001, nv04_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -741,7 +741,7 @@ nv4b_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv17_mc_new },
.mmu = nv41_mmu_new,
.mmu = { 0x00000001, nv41_mmu_new },
.pci = nv40_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -767,7 +767,7 @@ nv4c_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv4c_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -793,7 +793,7 @@ nv4e_chipset = {
.i2c = { 0x00000001, nv4e_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv4c_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -821,7 +821,7 @@ nv50_chipset = {
.i2c = { 0x00000001, nv50_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, nv50_mc_new },
.mmu = nv50_mmu_new,
.mmu = { 0x00000001, nv50_mmu_new },
.mxm = nv50_mxm_new,
.pci = nv46_pci_new,
.therm = nv50_therm_new,
@ -848,7 +848,7 @@ nv63_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv4c_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -874,7 +874,7 @@ nv67_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv4c_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -900,7 +900,7 @@ nv68_chipset = {
.i2c = { 0x00000001, nv04_i2c_new },
.imem = { 0x00000001, nv40_instmem_new },
.mc = { 0x00000001, nv44_mc_new },
.mmu = nv44_mmu_new,
.mmu = { 0x00000001, nv44_mmu_new },
.pci = nv4c_pci_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
@ -928,7 +928,7 @@ nv84_chipset = {
.i2c = { 0x00000001, nv50_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g84_pci_new,
.therm = g84_therm_new,
@ -960,7 +960,7 @@ nv86_chipset = {
.i2c = { 0x00000001, nv50_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g84_pci_new,
.therm = g84_therm_new,
@ -992,7 +992,7 @@ nv92_chipset = {
.i2c = { 0x00000001, nv50_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g92_pci_new,
.therm = g84_therm_new,
@ -1024,7 +1024,7 @@ nv94_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1056,7 +1056,7 @@ nv96_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1088,7 +1088,7 @@ nv98_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g98_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1120,7 +1120,7 @@ nva0_chipset = {
.i2c = { 0x00000001, nv50_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g84_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1152,7 +1152,7 @@ nva3_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, gt215_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gt215_pmu_new,
@ -1186,7 +1186,7 @@ nva5_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, gt215_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gt215_pmu_new,
@ -1219,7 +1219,7 @@ nva8_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, gt215_mc_new },
.mmu = g84_mmu_new,
.mmu = { 0x00000001, g84_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gt215_pmu_new,
@ -1252,7 +1252,7 @@ nvaa_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g98_mc_new },
.mmu = mcp77_mmu_new,
.mmu = { 0x00000001, mcp77_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1284,7 +1284,7 @@ nvac_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, g98_mc_new },
.mmu = mcp77_mmu_new,
.mmu = { 0x00000001, mcp77_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.therm = g84_therm_new,
@ -1316,7 +1316,7 @@ nvaf_chipset = {
.i2c = { 0x00000001, g94_i2c_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, gt215_mc_new },
.mmu = mcp77_mmu_new,
.mmu = { 0x00000001, mcp77_mmu_new },
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gt215_pmu_new,
@ -1352,7 +1352,7 @@ nvc0_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf100_pci_new,
.pmu = gf100_pmu_new,
@ -1389,7 +1389,7 @@ nvc1_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf106_pci_new,
.pmu = gf100_pmu_new,
@ -1425,7 +1425,7 @@ nvc3_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf106_pci_new,
.pmu = gf100_pmu_new,
@ -1461,7 +1461,7 @@ nvc4_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf100_pci_new,
.pmu = gf100_pmu_new,
@ -1498,7 +1498,7 @@ nvc8_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf100_pci_new,
.pmu = gf100_pmu_new,
@ -1535,7 +1535,7 @@ nvce_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf100_pci_new,
.pmu = gf100_pmu_new,
@ -1572,7 +1572,7 @@ nvcf_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf106_pci_new,
.pmu = gf100_pmu_new,
@ -1608,7 +1608,7 @@ nvd7_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf106_pci_new,
.therm = gf119_therm_new,
@ -1643,7 +1643,7 @@ nvd9_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gf100_ltc_new },
.mc = { 0x00000001, gf100_mc_new },
.mmu = gf100_mmu_new,
.mmu = { 0x00000001, gf100_mmu_new },
.mxm = nv50_mxm_new,
.pci = gf106_pci_new,
.pmu = gf119_pmu_new,
@ -1679,7 +1679,7 @@ nve4_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk104_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk104_pmu_new,
@ -1718,7 +1718,7 @@ nve6_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk104_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk104_pmu_new,
@ -1757,7 +1757,7 @@ nve7_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk104_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk104_pmu_new,
@ -1791,7 +1791,7 @@ nvea_chipset = {
.imem = { 0x00000001, gk20a_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gk20a_mmu_new,
.mmu = { 0x00000001, gk20a_mmu_new },
.pmu = gk20a_pmu_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
@ -1821,7 +1821,7 @@ nvf0_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk104_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk110_pmu_new,
@ -1859,7 +1859,7 @@ nvf1_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk104_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk110_pmu_new,
@ -1897,7 +1897,7 @@ nv106_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
@ -1935,7 +1935,7 @@ nv108_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gk104_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
@ -1973,7 +1973,7 @@ nv117_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gm107_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gm107_pmu_new,
@ -2009,7 +2009,7 @@ nv118_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gm107_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gk104_mmu_new,
.mmu = { 0x00000001, gk104_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gm107_pmu_new,
@ -2043,7 +2043,7 @@ nv120_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gm200_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gm200_mmu_new,
.mmu = { 0x00000001, gm200_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gm200_pmu_new,
@ -2081,7 +2081,7 @@ nv124_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gm200_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gm200_mmu_new,
.mmu = { 0x00000001, gm200_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gm200_pmu_new,
@ -2119,7 +2119,7 @@ nv126_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gm200_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gm200_mmu_new,
.mmu = { 0x00000001, gm200_mmu_new },
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gm200_pmu_new,
@ -2152,7 +2152,7 @@ nv12b_chipset = {
.imem = { 0x00000001, gk20a_instmem_new },
.ltc = { 0x00000001, gm200_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = gm20b_mmu_new,
.mmu = { 0x00000001, gm20b_mmu_new },
.pmu = gm20b_pmu_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
@ -2181,7 +2181,7 @@ nv130_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp100_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gm200_pmu_new,
@ -2221,7 +2221,7 @@ nv132_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
@ -2259,7 +2259,7 @@ nv134_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
@ -2297,7 +2297,7 @@ nv136_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
@ -2334,7 +2334,7 @@ nv137_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
@ -2372,7 +2372,7 @@ nv138_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gp100_mmu_new,
.mmu = { 0x00000001, gp100_mmu_new },
.therm = gp100_therm_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
@ -2404,7 +2404,7 @@ nv13b_chipset = {
.imem = { 0x00000001, gk20a_instmem_new },
.ltc = { 0x00000001, gp10b_ltc_new },
.mc = { 0x00000001, gp10b_mc_new },
.mmu = gp10b_mmu_new,
.mmu = { 0x00000001, gp10b_mmu_new },
.pmu = gp10b_pmu_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
@ -2433,7 +2433,7 @@ nv140_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, gp100_mc_new },
.mmu = gv100_mmu_new,
.mmu = { 0x00000001, gv100_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2477,7 +2477,7 @@ nv162_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, tu102_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2515,7 +2515,7 @@ nv164_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, tu102_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2554,7 +2554,7 @@ nv166_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, tu102_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2594,7 +2594,7 @@ nv167_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, tu102_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2632,7 +2632,7 @@ nv168_chipset = {
.imem = { 0x00000001, nv50_instmem_new },
.ltc = { 0x00000001, gp102_ltc_new },
.mc = { 0x00000001, tu102_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.therm = gp100_therm_new,
@ -2664,7 +2664,7 @@ nv170_chipset = {
.ibus = { 0x00000001, gm200_ibus_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, ga100_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.timer = gk20a_timer_new,
};
@ -2681,7 +2681,7 @@ nv172_chipset = {
.ibus = { 0x00000001, gm200_ibus_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, ga100_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.timer = gk20a_timer_new,
.disp = ga102_disp_new,
@ -2700,7 +2700,7 @@ nv174_chipset = {
.ibus = { 0x00000001, gm200_ibus_new },
.imem = { 0x00000001, nv50_instmem_new },
.mc = { 0x00000001, ga100_mc_new },
.mmu = tu102_mmu_new,
.mmu = { 0x00000001, tu102_mmu_new },
.pci = gp100_pci_new,
.timer = gk20a_timer_new,
.disp = ga102_disp_new,
@ -3248,7 +3248,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_SUBDEV_MMU , mmu);
_(NVKM_SUBDEV_MXM , mxm);
_(NVKM_SUBDEV_PCI , pci);
_(NVKM_SUBDEV_PMU , pmu);

8
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
View File

@ -415,9 +415,9 @@ nvkm_mmu = {
void
nvkm_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int index, struct nvkm_mmu *mmu)
enum nvkm_subdev_type type, int inst, struct nvkm_mmu *mmu)
{
nvkm_subdev_ctor(&nvkm_mmu, device, index, &mmu->subdev);
nvkm_subdev_ctor(&nvkm_mmu, device, type, inst, &mmu->subdev);
mmu->func = func;
mmu->dma_bits = func->dma_bits;
nvkm_mmu_ptc_init(mmu);
@ -428,10 +428,10 @@ nvkm_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int
nvkm_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int index, struct nvkm_mmu **pmmu)
enum nvkm_subdev_type type, int inst, struct nvkm_mmu **pmmu)
{
if (!(*pmmu = kzalloc(sizeof(**pmmu), GFP_KERNEL)))
return -ENOMEM;
nvkm_mmu_ctor(func, device, index, *pmmu);
nvkm_mmu_ctor(func, device, type, inst, *pmmu);
return 0;
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c
View File

@ -35,7 +35,8 @@ g84_mmu = {
};
int
g84_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
g84_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&g84_mmu, device, index, pmmu);
return nvkm_mmu_new_(&g84_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
View File

@ -84,7 +84,8 @@ gf100_mmu = {
};
int
gf100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gf100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&gf100_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gf100_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c
View File

@ -35,7 +35,8 @@ gk104_mmu = {
};
int
gk104_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gk104_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&gk104_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gk104_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
View File

@ -35,7 +35,8 @@ gk20a_mmu = {
};
int
gk20a_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gk20a_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&gk20a_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gk20a_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c
View File

@ -90,9 +90,10 @@ gm200_mmu_fixed = {
};
int
gm200_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gm200_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (device->fb->page)
return nvkm_mmu_new_(&gm200_mmu_fixed, device, index, pmmu);
return nvkm_mmu_new_(&gm200_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gm200_mmu_fixed, device, type, inst, pmmu);
return nvkm_mmu_new_(&gm200_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c
View File

@ -47,9 +47,10 @@ gm20b_mmu_fixed = {
};
int
gm20b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gm20b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (device->fb->page)
return nvkm_mmu_new_(&gm20b_mmu_fixed, device, index, pmmu);
return nvkm_mmu_new_(&gm20b_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gm20b_mmu_fixed, device, type, inst, pmmu);
return nvkm_mmu_new_(&gm20b_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c
View File

@ -37,9 +37,10 @@ gp100_mmu = {
};
int
gp100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gp100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true))
return gm200_mmu_new(device, index, pmmu);
return nvkm_mmu_new_(&gp100_mmu, device, index, pmmu);
return gm200_mmu_new(device, type, inst, pmmu);
return nvkm_mmu_new_(&gp100_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c
View File

@ -37,9 +37,10 @@ gp10b_mmu = {
};
int
gp10b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gp10b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true))
return gm20b_mmu_new(device, index, pmmu);
return nvkm_mmu_new_(&gp10b_mmu, device, index, pmmu);
return gm20b_mmu_new(device, type, inst, pmmu);
return nvkm_mmu_new_(&gp10b_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c
View File

@ -37,7 +37,8 @@ gv100_mmu = {
};
int
gv100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
gv100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&gv100_mmu, device, index, pmmu);
return nvkm_mmu_new_(&gv100_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c
View File

@ -35,7 +35,8 @@ mcp77_mmu = {
};
int
mcp77_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
mcp77_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&mcp77_mmu, device, index, pmmu);
return nvkm_mmu_new_(&mcp77_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
View File

@ -35,7 +35,8 @@ nv04_mmu = {
};
int
nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
nv04_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&nv04_mmu, device, index, pmmu);
return nvkm_mmu_new_(&nv04_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
View File

@ -47,11 +47,12 @@ nv41_mmu = {
};
int
nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
nv41_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (device->type == NVKM_DEVICE_AGP ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true))
return nv04_mmu_new(device, index, pmmu);
return nv04_mmu_new(device, type, inst, pmmu);
return nvkm_mmu_new_(&nv41_mmu, device, index, pmmu);
return nvkm_mmu_new_(&nv41_mmu, device, type, inst, pmmu);
}

7
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
View File

@ -62,11 +62,12 @@ nv44_mmu = {
};
int
nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
nv44_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
if (device->type == NVKM_DEVICE_AGP ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true))
return nv04_mmu_new(device, index, pmmu);
return nv04_mmu_new(device, type, inst, pmmu);
return nvkm_mmu_new_(&nv44_mmu, device, index, pmmu);
return nvkm_mmu_new_(&nv44_mmu, device, type, inst, pmmu);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View File

@ -71,7 +71,8 @@ nv50_mmu = {
};
int
nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
nv50_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu);
return nvkm_mmu_new_(&nv50_mmu, device, type, inst, pmmu);
}

8
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h
View File

@ -4,10 +4,10 @@
#define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev)
#include <subdev/mmu.h>
void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *,
int index, struct nvkm_mmu *);
int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *,
int index, struct nvkm_mmu **);
void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_mmu *);
int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_mmu **);
struct nvkm_mmu_func {
void (*init)(struct nvkm_mmu *);

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c
View File

@ -51,7 +51,8 @@ tu102_mmu = {
};
int
tu102_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
tu102_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&tu102_mmu, device, index, pmmu);
return nvkm_mmu_new_(&tu102_mmu, device, type, inst, pmmu);
}